uvm_reg_predictor——寄存器模型（十七）

// TITLE: Explicit Register Predictor
//------------------------------------------------------------------------------
//
// The <uvm_reg_predictor> class defines a predictor component,
// which is used to update the register model's mirror values
// based on transactions explicitly observed on a physical bus.
//------------------------------------------------------------------------------

class uvm_predict_s;
bit addr[uvm_reg_addr_t];
uvm_reg_item reg_item;
endclass

//------------------------------------------------------------------------------
//
// CLASS: uvm_reg_predictor
//
// Updates the register model mirror based on observed bus transactions
//
// This class converts observed bus transactions of type ~BUSTYPE~ to generic
// registers transactions, determines the register being accessed based on the
// bus address, then updates the register's mirror value with the observed bus
// data, subject to the register's access mode. See <uvm_reg::predict> for details.
//
// Memories can be large, so their accesses are not predicted.
//
//------------------------------------------------------------------------------

class uvm_reg_predictor #(type BUSTYPE=int) extends uvm_component;

`uvm_component_param_utils(uvm_reg_predictor#(BUSTYPE))

// Variable: bus_in
//
// Observed bus transactions of type ~BUSTYPE~ are received from this
// port and processed.
//
// For each incoming transaction, the predictor will attempt to get the
// register or memory handle corresponding to the observed bus address.
//
// If there is a match, the predictor calls the register or memory's
// predict method, passing in the observed bus data. The register or
// memory mirror will be updated with this data, subject to its configured
// access behavior--RW, RO, WO, etc. The predictor will also convert the
// bus transaction to a generic <uvm_reg_item> and send it out the
// ~reg_ap~ analysis port.
//
// If the register is wider than the bus, the
// predictor will collect the multiple bus transactions needed to
// determine the value being read or written.
//
uvm_analysis_imp #(BUSTYPE, uvm_reg_predictor #(BUSTYPE)) bus_in;

// Variable: reg_ap
//
// Analysis output port that publishes <uvm_reg_item> transactions
// converted from bus transactions received on ~bus_in~.
uvm_analysis_port #(uvm_reg_item) reg_ap;

// Variable: map
//
// The map used to convert a bus address to the corresponding register
// or memory handle. Must be configured before the run phase.
//
uvm_reg_map map;

// Variable: adapter
//
// The adapter used to convey the parameters of a bus operation in
// terms of a canonical <uvm_reg_bus_op> datum.
// The <uvm_reg_adapter> must be configured before the run phase.
//
uvm_reg_adapter adapter;

// Function: new
//
// Create a new instance of this type, giving it the optional ~name~
// and ~parent~.
//
function new (string name, uvm_component parent);
endfunction

// This method is documented in uvm_object
static string type_name = "";
virtual function string get_type_name();
endfunction

// Function: pre_predict
//
// Override this method to change the value or re-direct the
// target register
//
virtual function void pre_predict(uvm_reg_item rw);
endfunction

local uvm_predict_s m_pending[uvm_reg];

// Function- write
//
// not a user-level method. Do not call directly. See documentation
// for the ~bus_in~ member.
//
virtual function void write(BUSTYPE tr);
endfunction

// Function: check_phase
//
// Checks that no pending register transactions are still queued.

virtual function void check_phase(uvm_phase phase);
endfunction

endclass