FPGA- 序列检测器

FPGA- 序列检测器

序列检测器是时序数字电路设计中经典的教学范例。下面我将用Verilog HDL语言来描述、仿真并实现它。
本次设计实现：设计一个“10010”序列的检测器。设x为数字码流输入，z为检测标记输出，高电平表示“发现指定序列”，低电平表示“没有发现指定序列”。本次设计的码流设置为data=20'b1100_1001_0000_1001_0100.其状态转换图如下面的图片。

module seqdet(x,z,clk,rest);
input x;
input clk;
input rest;
output reg z;

parameter s0 = 6'b000_001,
s1 = 6'b000_010,
s2 = 6'b000_100,
s3 = 6'b001_000,
s4 = 6'b010_000,
s5 = 6'b100_000;

reg [5:0] state;
always@(posedge clk or negedge rest)
if(!rest)
begin
state <= s0;
z <= 0;
end
else
case(state)
s0:begin
if(x)
begin
state <= s1;
z <= 0;
end
else
begin
state <= s0;
z <= 0;
end
end
s1:begin
if(x)
begin
state <= s1;
z <= 0;
end
else
begin
state <= s2;
z <= 0;
end
end
s2:begin
if(x)
begin
state <= s1;
z <= 0;
end
else
begin
state <= s3;
z <= 0;
end
end
s3:begin
if(x)
begin
state <= s4;
z <= 0;
end
else
begin
state <= s0;
z <= 0;
end
end
s4:begin
if(x)
begin
state <= s1;
z <= 0;
end
else
begin
state <= s5;
z <= 1;
end
end
s5:begin
if(x)
begin
state <= s1;
z <= 0;
end
else
begin
state <= s0;
z <= 0;
end
end
default: begin state <= s0;z <= 0;end
endcase
endmodule

`timescale 1 ns/1 ns
module seqdet_tb;
wire x;
reg clk;
reg rest;
reg [23:0] data;
wire z;
assign x = data[23];
seqdet seqdet0(
.x(x),
.z(z),
.clk(clk),
.rest(rest)
);
parameter temp=20;
initial
begin
clk = 0;rest = 1;
#temp rest = 0;
#(temp*20) rest = 1;
data = 20'b1100_1001_0000_1001_0100;
#(temp*200) $stop;
end
always #(temp/2) clk = ~clk;
always@(posedge clk)
#2 data={data[22:0],data[23]};
endmodule