【iCore1S 双核心板_FPGA】例程十：乘法器实验——乘法器的使用

module MULT(
input CLK_12M,
output FPGA_LEDR
);
//------------------rst_n-------------------------//
reg [3:0]cnt_rst;
reg rst_n;

always@(posedge CLK_12M) //产生复位信号
begin
if(cnt_rst==4'd15)
begin
cnt_rst = 4'd15;
rst_n =1'd1;
end
else cnt_rst <= cnt_rst + 1'd1;
end

//--------------------CLK_10Hz--------------------//
reg [20:0]cnt;
reg CLK_10HZ;

always@(posedge CLK_12M)
begin
if(!rst_n)
begin
CLK_10HZ <= 1'd0;
cnt <= 21'd0;
end
else if(cnt==21'd1199_999)
begin
CLK_10HZ <=~CLK_10HZ;
cnt <= 21'd0;
end
else cnt <= cnt + 1'd1;
end

//----------------data_in&data_out---------------//
reg [7:0]a;

always@(posedge CLK_10HZ)
begin
if(!rst_n)
a<= 8'd0;
else if(a==8'd255)
a <= 8'd0;
else a <= a + 1'd1;
end

//------------------my_mult--------------------//
wire [15:0]out;

my_mult u1(
.dataa(a),
.datab(a),
.result(out)
);

assign FPGA_LEDR = out[6];

//-------------==---endmodule------------------//
endmodule