gdb + openocd 调试嵌入式软件

1.openocd是硬件层次的调试，gdb是源码层次的调试。

2.在gdb中可以使用monitor发送openocd的命令，例如monitor reset;halt

3.JTAG有4种复位方式：

There are many kinds of reset possible through JTAG, but they may not

all work with a given board and adapter. That’s part of why reset

configuration can be error prone.

System Reset, the SRST hardware signal resets all chips connected to the JTAG adapter, such as processors, power management chips, and I/O controllers. Normally resets triggered with this signal behave exactly like pressing a RESET button.

JTAG TAP Reset, the TRST hardware signal resets just the TAP

controllers con- nected to the JTAG adapter. Such resets should not be

visible to the rest of the system; resetting a device’s TAP controller

just puts that controller into a known state.

Emulation Reset, many devices can be reset through JTAG commands.

These resets are often distinguishable from system resets, either

explicitly (a “reset reason” register says so) or implicitly (not all

parts of the chip get reset).

Other Resets, system-on-chip devices often support several other

types of reset. You may need to arrange that a watchdog timer stops

while debugging, preventing a watchdog reset. There may be individual

module resets.

In the best case, OpenOCD can hold SRST, then reset the TAPs via TRST and send commands through JTAG to halt the CPU at the reset vector before the 1st instruction is executed. Then when it finally releases

the SRST signal, the system is halted under debugger control before

any code has executed. This is the behavior required to support the

reset halt and reset init commands; after reset init a board-specific

script might do things like setting up DRAM. (See [Reset Command],

page 97.)