VHDL inout与buffer
2016-08-26 18:36
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VHDL中BUFFER与INOUT有什么区别呢?首先INOUT完全是双向的,也就是
INOUT:=IN+OUT,对INOUT属性的PIN既可以写出也可以读入,他有2个寄存器,如
...
port(a:inout std_logic);
...
signal ccc,ddd:bit
process(clk)
begin
...
a<=ccc;此时端口a为CCC的值
...
ddd<=a;读入端口a此时的信号
BUFFER: 一般比较少用,它实际上输出的功能与out一样,他只有1个寄存器,而此时读入的却是上次从该口输出的值,比如:
port(a:buffer std_logic);
...
signal ccc,ddd:bit
process(clk)
begin
...
a<=ccc;此时端口a为CCC的值
...
ddd<=a;读入到ddd的值其实等于ccc的值。(如果中间没有给a赋新值的话)。
INOUT:=IN+OUT,对INOUT属性的PIN既可以写出也可以读入,他有2个寄存器,如
...
port(a:inout std_logic);
...
signal ccc,ddd:bit
process(clk)
begin
...
a<=ccc;此时端口a为CCC的值
...
ddd<=a;读入端口a此时的信号
BUFFER: 一般比较少用,它实际上输出的功能与out一样,他只有1个寄存器,而此时读入的却是上次从该口输出的值,比如:
port(a:buffer std_logic);
...
signal ccc,ddd:bit
process(clk)
begin
...
a<=ccc;此时端口a为CCC的值
...
ddd<=a;读入到ddd的值其实等于ccc的值。(如果中间没有给a赋新值的话)。
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