您的位置：首页 > 其它

keypad 错误

2016-05-07 13:02 218 查看
always@(posedge CLK or negedge nRESET)
begin
if(!nRESET)
begin

end

else
begin
if(key_en)
begin
case (key_value_1)
7'b0001_001: key_value <= 4'd1;  //1
7'b0010_001: key_value <= 4'd4;  //4
7'b0100_001: key_value <= 4'd7;  //7
7'b1000_001: key_value <= 4'd0;  //*
7'b0001_010: key_value <= 4'd2;  //2
7'b0010_010: key_value <= 4'd5;  //5
7'b0100_010: key_value <= 4'd8;  //8
7'b1000_010: key_value <= 4'd0;  //0
7'b0001_100: key_value <= 4'd3;  //3
7'b0010_100: key_value <= 4'd6;  //6
7'b0100_100: key_value <= 4'd9;  //9
7'b1000_100: key_value <= 4'd0;  //#
endcase
end
else
begin

end
end
end

结果正确

always@(posedge CLK or negedge nRESET)
begin
if(!nRESET)
begin
key_value <= 4'd0;
end

else
begin
if(key_en)
begin
case (key_value_1)
7'b0001_001: key_value <= 4'd1;  //1
7'b0010_001: key_value <= 4'd4;  //4
7'b0100_001: key_value <= 4'd7;  //7
7'b1000_001: key_value <= 4'd0;  //*
7'b0001_010: key_value <= 4'd2;  //2
7'b0010_010: key_value <= 4'd5;  //5
7'b0100_010: key_value <= 4'd8;  //8
7'b1000_010: key_value <= 4'd0;  //0
7'b0001_100: key_value <= 4'd3;  //3
7'b0010_100: key_value <= 4'd6;  //6
7'b0100_100: key_value <= 4'd9;  //9
7'b1000_100: key_value <= 4'd0;  //#
endcase
end
else
begin
key_value <= 4'd0;
end
end
end

结果错误
内容来自用户分享和网络整理，不保证内容的准确性，如有侵权内容，可联系管理员处理 点击这里给我发消息
标签：  fpga Xilinx 数字钟 Verilog
相关文章推荐
新的分享
章节导航