Verilog (一) assignment, register and net

reg  [1:0]  data_sync;

always @ (posedge clk or posedge rst)
begin
if (rst)
data_sync  <=  2'b00;
else
data_sync  <= {data_sync[0], data_in};
end

assign  data_out  =  data_sync[1];

synchronizer