FPGA之流水灯

module move_led
(
clk,
rst,
led
);

input clk;
input rst;

output [5:0]led;

reg [23:0]count;
always @(posedge clk or negedge rst)
begin
if(!rst) count <= 24'd0;
else if(count == 24'hffffff) count <= 24'd0;
else count <= count + 1'd1;
end

reg [5:0]led_r;
always @(posedge clk or negedge rst)
begin
if(!rst) led_r <= 6'b111_110;
else if (count == 24'hfffffe) led_r <= {led_r[4:0],led_r[5]};
else led_r <= led_r;
end

assign led = led_r;

endmodule