RAM-based Shift Register problem in Vivado 2014.4

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RAM-based Shift Register problem in Vivado 2014.4

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elikelik

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Posts: 3

Registered: ‎09-24-2013

RAM-based Shift Register problem in Vivado 2014.4

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‎12-31-2014 12:30 AM

Hi,

 

I have a RAM-based Shift Register in my design, which gives me the following Critical Error when trying to open the implemented design:

 

[EDIF 20-80] cannot connect net 'd[0]' to pin 'lls_speed.s3_v2_v4_v5_lls.gen_width[0].gen_depth[0].gen_only.i_lls_only/D[0]' in cell 'shift_ram_16x16_s_c_shift_ram_v12_0_legacy_HD1337'. This pin is already connected
to net 'mux_in[0,0]'. The new connection will be ignored.

 

The same IP (and the same design) was used in Vivado 2014.2 with no problem.

When trying to compile the exact same design in Vivado 2014.4 (after the IP was upgraded to Version 12.0 Rev. 5), I got the above message.

 

This Critical Error prevents the generation of a Bitstream file.

 

The IP is configured as:
Variable Length Lossless
Optimized to speed
Register Last Bit is checked (without CE)
Dimensions are 16x16
Initialized to 0 without a COE File
Power-on Reset value is 0
None of the Synchronous Settings (SCLR, SSET or SINIT) is activated

Any help is greatly appreciated.

 

Thanks,

    Elik

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jefedenorsk

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Posts: 28

Registered: ‎08-06-2012

Re: RAM-based Shift Register problem in Vivado 2014.4

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‎01-13-2015 12:32 PM

Did you figure this out?  I just updated to 2014.4 and a blockram core I'm using started throwing the same error.

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jefedenorsk

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Posts: 28

Registered: ‎08-06-2012

Re: RAM-based Shift Register problem in Vivado 2014.4

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‎01-13-2015 12:44 PM

My error : ERROR: [EDIF 20-80] Cannot connect net 'douta[9]' to pin 'ramloop[33].ram.r/douta[0]' in cell 'data_config_bram_131072by10blk_mem_gen_generic_cstr_HD2945'. This pin is
already connected to net 'n_0_ramloop[32].ram.r'. The new connection will be ignored.

I'll also add that I'm using synplify_pro for synthesis of the RTL connected to this core through a blackbox and using the core dcp output in Vivado. Looking at the code I don't see anything that would cause this, especially if it worked fine before upgrading
(from 2013.4 in my case).

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 balkris

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Posts: 1,876

Registered: ‎08-01-2008

Re: RAM-based Shift Register problem in Vivado 2014.4

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‎01-13-2015 11:09 PM

have you guys tried with Vivado synthesis tool. I believe you can regenerate the core with latest version in place of migrating from old versions.
Thanks and Regards

Balkrishan

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 balkris

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Posts: 1,876

Registered: ‎08-01-2008

Re: RAM-based Shift Register problem in Vivado 2014.4

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‎01-13-2015 11:22 PM

send me the test case to reproduce this issue . I am not aware of any such known issue with core. You may try with Vivado synthesis tool
Thanks and Regards

Balkrishan

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jeremy.weagley

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Posts: 4

Registered: ‎08-13-2012

Re: RAM-based Shift Register problem in Vivado 2014.4

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‎05-29-2015 01:52 PM

I'm having a similar problem. I created a FFT core using the IP catalog in Vivado 2014.4. This FFT core works properly in a design where it is the only FFT, but when I try to replicate the core several times in another design, I get the following error:

 

[EDIF 20-80] Cannot connect net 'd[0]' to pin 'lls_area.depth_lteq_1srl.gen_srl[0].ills_only/D[0]' in cell 'hf_fft_c_shift_ram_v12_0_legacy__parameterized14__1_HD3252'. This pin is already connected to net 'p_28_out'. The new connection
will be ignored.

 

Any idea what the problem might be here? If you need any additional information, let me know.

 

Thanks,

Jeremy

 

 

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jeremy.weagley

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Registered: ‎08-13-2012

Re: RAM-based Shift Register problem in Vivado 2014.4

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‎06-11-2015 10:52 AM

For what it's worth, I was able to find a workaround to this problem. I created multiple versions of the same FFT and instantiated each of those rather than instantiating the same FFT multiple times. So rather than:

 

fft_0_inst: hf_fft

 

fft_1_inst: hf_fft

 

fft_2_inst: hf_fft

 

I now have:

 

fft_0_inst: hf_fft_0

 

fft_1_inst: hf_fft_1

 

fft_2_inst: hf_fft_2

 

Hope this helps

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durakt

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Posts: 5

Registered: ‎01-13-2015

Re: RAM-based Shift Register problem in Vivado 2014.4

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‎07-30-2015 11:19 AM

I have only one instance of the fft core but I am getting this same error message (tops out at 100 errors during bitstream generation)

[EDIF 20-80] Cannot connect net 'd[0]' to pin 'lls_area.depth_lteq_1srl.gen_srl[0].i_lls_only/D[0]' in cell 'fft_8k_RTcnfg_12_12_c_shift_ram_v12_0_legacy__parameterized16__1_HD1500'. This pin is already connected to net 'p_20_out'.
The new connection will be ignored. ["c:/Users/tdurak.ANNARBOR/xlnx_des/DU_f/vivado/project/td4_bf_lpbk/td4_bf_lpbk.runs/impl_1/.Xil/Vivado-1216-tdurak-e6520/dcp/FPGA_top.edf":2281135]

 

I do have the fft data output splitting to two identical IP Core Fifos.  I could build these as two inependent fifo cores (similar to what jeremy did with his FFT core), but I feel like I would just be fishing, and that takes a longggg time.

 

Does anyone have any suggestions?

 

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durakt

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Posts: 5

Registered: ‎01-13-2015

Re: RAM-based Shift Register problem in Vivado 2014.4

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‎07-30-2015 11:21 AM

Note I am using Vivado 2014.3.1

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