VHDL实现加法器

//全加法器

library ieee;

use ieee.std_logic_1164.all;

entity alladder is

port(

A,B,Cin:in std_logic;

S,Cout:out std_logic

);

end entity alladder;

architecture adderfunc of alladder is

begin

Cout<=((A xor B) AND Cin) OR (A AND B);

END;

//四位并行加法器

library ieee;

use ieee.std_logic_1164.all;

entity sequenadder is

port(

A:IN BIT_VECTOR(3 DOWNTO 0);

B:IN BIT_VECTOR(3 DOWNTO 0);

Cin:IN BIT;

S:OUT BIT_VECTOR(4 DOWNTO 0)

);

END;

ARCHITECTURE SEQUENFUNC OF sequenadder IS

SIGNAL SIN1:BIT;

SIGNAL SIN2:BIT;

SIGNAL SIN3:BIT;

COMPONENT alladder IS

PORT(

A,B,Cin:IN BIT;

S,Cout:OUT BIT

);

END COMPONENT;

BEGIN

G1:alladder port map(A=>A(0),B=>B(0),Cin=>Cin,S=>S(0),Cout=>SIN1);

G2:alladder port map(A=>A(1),B=>B(1),Cin=>SIN1,S=>S(1),Cout=>SIN2);

G3:alladder port map(A=>A(2),B=>B(2),Cin=>SIN2,S=>S(2),Cout=>SIN3);

G4:alladder port map(A=>A(3),B=>B(3),Cin=>SIN3,S=>S(3),Cout=>S(4));

END;

//超前进位加法器

library ieee;

use ieee.std_logic_1164.all;

entity fastadder is

port(

A:IN BIT_VECTOR(3 DOWNTO 0);

B:IN BIT_VECTOR(3 DOWNTO 0);

CIN:IN BIT;

S:OUT BIT_VECTOR(4 DOWNTO 0)

);

END;

ARCHITECTURE FASTADDFUNC OF fastadder IS

SIGNAL COUT0:BIT;

SIGNAL COUT1:BIT;

SIGNAL COUT2:BIT;

BEGIN

COUT0<=(A(0) AND B(0))OR(CIN AND (A(0) OR B(0)));

COUT1<=(A(1) AND B(1))OR(COUT0 AND (A(1) OR B(1)));

COUT2<=(A(2) AND B(2))OR(COUT1 AND (A(2) OR B(2)));

S(4)<=(A(3) AND B(3))OR(COUT2 AND (A(3) OR B(3)));

S(0)<=A(0) XOR B(0) XOR CIN;

S(1)<=A(1) XOR B(1) XOR COUT0;

S(2)<=A(2) XOR B(2) XOR COUT1;

S(3)<=A(3) XOR B(3) XOR COUT2;

END ;