两位16进制加减可逆计数器
2015-06-13 09:01
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本例使用VHDL编写的两位十六进制(两个七段数码管显示,每个数码管范围是0~F)加减可逆计数器。其中所用实验箱是武汉大学的教学实验箱,其它实验箱请自行变通。
转载请注明出处,谢谢!以下是完整代码:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter6 is
port(clk0,clk1,clk2,din,en,rst,direc:in std_logic; --direc为方向控制,1加法计数,0减法计数
dout:out std_logic_vector(7 downto 0);
scan:out std_logic_vector(5 downto 0));
end counter6;
architecture Behavioral of counter6 is
signal c,f1,f2, f3,f4,f5,f6,fclk,fd,f:std_logic:='0';
signal data1,data2,dataout,fclk1:std_logic_vector(3 downto 0);
signal temp:std_logic;
begin
process(clk1)
begin
if clk1'event and clk1='1' then
fclk1<= fclk1+1;
end if;
end process;
fd<=fclk1(3);
process(fd)
begin
if fd'event and fd='1' then
if din = '0' then c<='1';
else c<='0';
end if;
end if;
end process;
process(clk0)
begin
if clk0'event and clk0='1' then
fclk<=( not fclk);
end if;
end process;
f1<=(c and en)or (fclk and not en );
process(f1) --低位计数
begin
if rst='1' then data1<="0000";
elsif f1'event and f1='1' then
if direc = '1' then -- 加法计数
if data1="1111" then
f2<='1';data1<="0000"; --产生的f2为进位信号
else data1<=data1+1;f2<='0';
end if;
else -- 减法计数
if data1="0000" then
f2<='1';data1<="1111"; --产生的f2是借位信号
else data1<=data1-1;f2<='0';
end if;
end if;
end if;
end process;
process(f2) --高位计数
begin
if rst='1' then data2<="0000";
elsif f2'event and f2='1' then
if direc = '1' then -- 加法计数
if data2="1111" then
data2<="0000"; --产生的f2为进位信号
else data2<=data2+1;
end if;
else -- 减法计数
if data2="0000" then
data2<="1111"; --产生的f2是借位信号
else data2<=data2-1;
end if;
end if;
end if;
end process;
process(clk2)
begin
if clk2'event and clk2='1' then
if temp = '1' then temp <='0';
else
temp<= '1';
end if;
end if;
end process;
process(temp)
begin
case temp is
when '0' => dataout<=data1;scan<="000001";
when '1' => dataout<=data2;scan<="000010";
when others =>null;
end case;
case dataout is
when "0000" => dout <="00111111" ; --0
when "0001" => dout <="00000110" ; --1
when "0010" => dout <="01011011" ; --2
when "0011" => dout <="01001111" ; --3
when "0100" => dout <="01100110" ; --4
when "0101" => dout <="01101101" ; --5
when "0110" => dout <="01111101" ; --6
when "0111" => dout <="00000111" ; --7
when "1000" => dout <="01111111" ; --8
when "1001" => dout <="01101111" ; --9
when "1010" => dout <="01110111" ; --a
when "1011" => dout <="01111100" ; --b
when "1100" => dout <="00111001" ; --c
when "1101" => dout <="01011110" ; --d
when "1110" => dout <="01111001" ; --e
when "1111" => dout <="01110001" ; --f
when others => dout<="00000000";
e
4000
nd case;
end process;
end Behavioral;
接下来是引脚分配图:
转载请注明出处,谢谢!以下是完整代码:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter6 is
port(clk0,clk1,clk2,din,en,rst,direc:in std_logic; --direc为方向控制,1加法计数,0减法计数
dout:out std_logic_vector(7 downto 0);
scan:out std_logic_vector(5 downto 0));
end counter6;
architecture Behavioral of counter6 is
signal c,f1,f2, f3,f4,f5,f6,fclk,fd,f:std_logic:='0';
signal data1,data2,dataout,fclk1:std_logic_vector(3 downto 0);
signal temp:std_logic;
begin
process(clk1)
begin
if clk1'event and clk1='1' then
fclk1<= fclk1+1;
end if;
end process;
fd<=fclk1(3);
process(fd)
begin
if fd'event and fd='1' then
if din = '0' then c<='1';
else c<='0';
end if;
end if;
end process;
process(clk0)
begin
if clk0'event and clk0='1' then
fclk<=( not fclk);
end if;
end process;
f1<=(c and en)or (fclk and not en );
process(f1) --低位计数
begin
if rst='1' then data1<="0000";
elsif f1'event and f1='1' then
if direc = '1' then -- 加法计数
if data1="1111" then
f2<='1';data1<="0000"; --产生的f2为进位信号
else data1<=data1+1;f2<='0';
end if;
else -- 减法计数
if data1="0000" then
f2<='1';data1<="1111"; --产生的f2是借位信号
else data1<=data1-1;f2<='0';
end if;
end if;
end if;
end process;
process(f2) --高位计数
begin
if rst='1' then data2<="0000";
elsif f2'event and f2='1' then
if direc = '1' then -- 加法计数
if data2="1111" then
data2<="0000"; --产生的f2为进位信号
else data2<=data2+1;
end if;
else -- 减法计数
if data2="0000" then
data2<="1111"; --产生的f2是借位信号
else data2<=data2-1;
end if;
end if;
end if;
end process;
process(clk2)
begin
if clk2'event and clk2='1' then
if temp = '1' then temp <='0';
else
temp<= '1';
end if;
end if;
end process;
process(temp)
begin
case temp is
when '0' => dataout<=data1;scan<="000001";
when '1' => dataout<=data2;scan<="000010";
when others =>null;
end case;
case dataout is
when "0000" => dout <="00111111" ; --0
when "0001" => dout <="00000110" ; --1
when "0010" => dout <="01011011" ; --2
when "0011" => dout <="01001111" ; --3
when "0100" => dout <="01100110" ; --4
when "0101" => dout <="01101101" ; --5
when "0110" => dout <="01111101" ; --6
when "0111" => dout <="00000111" ; --7
when "1000" => dout <="01111111" ; --8
when "1001" => dout <="01101111" ; --9
when "1010" => dout <="01110111" ; --a
when "1011" => dout <="01111100" ; --b
when "1100" => dout <="00111001" ; --c
when "1101" => dout <="01011110" ; --d
when "1110" => dout <="01111001" ; --e
when "1111" => dout <="01110001" ; --f
when others => dout<="00000000";
e
4000
nd case;
end process;
end Behavioral;
接下来是引脚分配图:
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