数字电路设计之恢复余数除法器的verilog实现

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:   SMIE
// Engineer:  陈钰
// Create Date:    17:21:46 10/05/2014 
// Design Name:    divider
// Module Name:    divider_res 
// Project Name:   divider
// Target Devices: spartan 6
// Tool versions:  xilinx
// Description:    it's a divider that can restore remainder 
// Revision 0.01 - File Created
// Additional Comments: 转载请注明出处
//////////////////////////////////////////////////////////////////////////////////
module divider_res(a,b,start,clk,rst,q,r,busy,ready,cnt);
	input   [31:0]  a;  //divident 
	input   [15:0]  b;  //divisor
	input           start,rst,clk;
	output  [31:0]  q; //quotient
	output  [15:0]  r; //remainder
	output          busy,ready;
	output  [4:0]   cnt;
	wire    [31:0]  a;
	wire    [15:0]  b;
	wire            ready,start,rst,clk;
	wire    [31:0]  q;
	wire    [15:0]  r;
	wire    [16:0]  sub_out;
	wire    [15:0]  mux_out;
	reg     [31:0]  reg_quotient;
	reg     [15:0]  reg_remainder;
	reg     [15:0]  reg_b;
	reg     [4:0]   cnt;
	reg             busy,busy2;
	
	always@(posedge clk)
	begin
		if(rst)
			begin
				cnt   <= 0;
				busy  <= 0;
				busy2 <= 0; 
			end
		else
			begin
				busy2 <= busy; //1 delay for busy
				if(start)
					begin
						reg_quotient  <= a;
						reg_remainder <= 16'b0;
						reg_b         <= b;
						cnt           <= 5'b0;
						busy          <= 1'b1;
					end
				else
				if(busy)         //execution 32 cycles
					begin
						reg_quotient  <= {reg_quotient[30:0],~sub_out[16]}; //1 bit quotient
						reg_remainder <= mux_out;   
						cnt  <= cnt + 1;
						if(cnt == 5'h1f)
							busy <= 0;//finish
					end
			end
	end
	
	assign ready   = (~busy)&busy2;
	assign sub_out = {r,q[31]} - {1'b0,reg_b};                  //sub_out
	assign mux_out = sub_out[16]?{r[14:0],q[31]}:sub_out[15:0]; //restore or not
	assign q       = reg_quotient;
	assign r       = reg_remainder;
	
endmodule