数字电路设计之低功耗设计方法一：bus总线翻转

Businveter：就是IO的输入输出的变化会导致大量的动态功耗，若采用一个inveter位表示一个输入输出是否需要翻转，可以使得IO翻转大大减少，从而动态功耗也就降低了。具体的操作就是当hanming距离大于bus的bit数加上inveter的位数的变化位数的一半的时候那就翻转，invetert置为1。Haming距离就是前一个输出与当前输出的需要翻转的个数。

首先是没有Bus-inveter的verilog：

module Busconveter(

clk,

bus_input,

bus_output

);

input wire clk;

input wire [15:0]bus_input;

output reg [15:0]bus_output;

always@(posedge clk)

bus_output <= bus_input;

endmodule

接着是有Bus-invetert技术的代码：

module Bus_inveter(

clr,

clk,

bus_input,

bus_output,

inveter

);



input wire clr;

input wire clk;

input wire [15:0]bus_input;

output reg [15:0]bus_output;

output reg inveter;

reg [15:0]temp;

reg [3:0]count;



always@(posedge clk,posedge clr) //如果count(Hamming distance)>Bus_input and pre_output,翻转

if(clr)

begin

bus_output <= 16'b0;

end

else

begin

if(inveter == 1)

begin

bus_output <= ~bus_input;

end

else

begin

bus_output <= bus_input;

end

end



always@(posedge clk,posedge clr)

if(clr)

begin

count <= 4'b0;

inveter <= 1'b0;

end

else

begin

count = 0;

if((bus_input[0]^temp[0]) == 1'b1)

count = count + 1;

if((bus_input[1]^temp[1]) == 1'b1)

count = count + 1;

if((bus_input[2]^temp[2]) == 1'b1)

count = count + 1;

if((bus_input[3]^temp[3]) == 1'b1)

count = count + 1;

if((bus_input[4]^temp[4]) == 1'b1)

count = count + 1;

if((bus_input[5]^temp[5]) == 1'b1)

count = count + 1;

if((bus_input[6]^temp[6]) == 1'b1)

count = count + 1;

if((bus_input[7]^temp[7]) == 1'b1)

count = count + 1;

if((bus_input[8]^temp[8]) == 1'b1)

count = count + 1;

if((bus_input[9]^temp[9]) == 1'b1)

count = count + 1;

if((bus_input[10]^temp[10]) == 1'b1)

count = count + 1;

if((bus_input[11]^temp[11]) == 1'b1)

count = count + 1;

if((bus_input[12]^temp[12]) == 1'b1)

count = count + 1;

if((bus_input[13]^temp[13]) == 1'b1)

count = count + 1;

if((bus_input[14]^temp[14]) == 1'b1)

count = count + 1;

if((bus_input[15]^temp[15]) == 1'b1)

count = count + 1;

begin

if(count >= 8)

begin

inveter <= 1'b1;

end

else

begin

inveter <= 1'b0;

end

end

end

always@(posedge clk,posedge clr)

if(clr)

temp <= 16'b0;

else

temp <= bus_output;

endmodule

仿真代码：

module test;

// Inputs

reg clr;

reg clk;

reg [15:0] bus_input;

// Outputs

wire [15:0] bus_output;

wire inveter;

// Instantiate the Unit Under Test (UUT)

Bus_inveter uut (

.clr(clr),

.clk(clk),

.bus_input(bus_input),

.bus_output(bus_output),

.inveter(inveter)

);

always #50 clk = ~clk;



initial begin

$dumpfile("Bus_conveter.vcd");

$dumpvars(1,test.uut);

// Initialize Inputs

bus_input = 0;

clk = 0;

clr = 1;

// Wait 100 ns for global reset to finish

#100;

clr = 0;

bus_input = 16'hffff;

#100;

bus_input = 16'heeee;

#100;

bus_input = 16'h1111;

#100;

bus_input = 16'h1100;

#100;

bus_input = 16'hffec;

#100;

bus_input = 16'h0000;

#100;

bus_input = 16'hedef;

#100;

bus_input = 16'h1234;

#100;

bus_input = 16'h4356;

#100;

bus_input = 16'h7870;

#100;

bus_input = 16'h2e34;

#100;

bus_input = 16'hc311;

#100;

bus_input = 16'h2313;

#100;

bus_input = 16'h2313;

#100;

bus_input = 16'h1111;

#100;

bus_input = 16'hffff;

#100;

bus_input = 16'h2222;

#100;

bus_input = 16'h12de;

#100;

bus_input = 16'hffff;

#100;

bus_input = 16'hf11f;

#100;

bus_input = 16'hf11f;

// Add stimulus here

end



endmodule