VHDL：时序逻辑电路实验-手动设置8位检测码的序列检测器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity kledjc is
port(KBdata: in STD_LOGIC;
KBCLK: in STD_LOGIC;
CLKIN: in STD_LOGIC;
led: out std_logic_vector(7 downto 0);
rst: in std_logic;
n: in std_logic_vector(7 downto 0);
jgout: out std_logic_vector(3 downto 0));
end kledjc;

architecture behv of kledjc is
signal CLK: std_logic;
signal M: std_logic_vector(9 downto 0);
signal S: std_logic_vector(9 downto 0);
signal NUM: std_logic_vector(7 downto 0);
signal q: integer range 0 to 8;

begin
process(CLKIN,RST)
begin
if(RST='0') then
CLK<='1';
elsif(CLKIN'event and CLKIN='1') then
if KBCLK='0' then
CLK<=KBCLK;
else
CLK<='1';
end if;
end if;
end process;

process(CLK,KBdata,S)
begin
if(CLK'event and CLK='0') then
M<=KBdata & S(9 downto 1);
end if;
end process;

process(clk,M,S)
begin
if(CLK'event and CLK='1') then
S<=M;
end if;
case S(7 downto 0) is
when "00010110"=>NUM<="00000110";
when "00011110"=>NUM<="01011011";
when "00100110"=>NUM<="01001111";
when "00100101"=>NUM<="01100110";
when "00101110"=>NUM<="01101101";
when "00110110"=>NUM<="01111101";
when "00111101"=>NUM<="00000111";
when "00111110"=>NUM<="01111111";
when "01000110"=>NUM<="01101111";
when "01000101"=>NUM<="00111111";
when "00011100"=>NUM<="01110111";
when "00110010"=>NUM<="01111100";
when "00100001"=>NUM<="00111001";
when "00100011"=>NUM<="01011110";
when "00100100"=>NUM<="01111001";
when "00101011"=>NUM<="01110001";
when others=>NUM<="00000000";
end case;
led<=NUM;
end process;

process(q)
begin
if s(7 downto 0)=n(7 downto 0) then jgout<="1010";  q<=1;
else jgout<="1011";  q<=0;
end if;
end process;
end Behv;