FPGA+NIOS II 平台 DM9000最新驱动

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#include <stdio.h>

#include "DM9000A.H"

#include "basic_io.h"

//-------------------------------------------------------------------------

void iow(unsigned int reg, unsigned int data)

{

usleep(STD_DELAY);

IOWR(DM9000A_BASE,IO_addr,reg);

usleep(STD_DELAY);

IOWR(DM9000A_BASE,IO_data,data);

}

//-------------------------------------------------------------------------

unsigned int ior(unsigned int reg)

{

usleep(STD_DELAY);

IOWR(DM9000A_BASE,IO_addr,reg);

usleep(STD_DELAY);

return IORD(DM9000A_BASE,IO_data);

}

//-------------------------------------------------------------------------

void phy_write (unsigned int reg, unsigned int value)

{

/* set PHY register address into EPAR REG. 0CH */

iow(0x0C, reg | 0x40); /* PHY register address setting, and DM9000_PHY offset = 0x40 */

/* fill PHY WRITE data into EPDR REG. 0EH & REG. 0DH */

iow(0x0E, ((value >> 8) & 0xFF)); /* PHY data high_byte */

iow(0x0D, value & 0xFF); /* PHY data low_byte */

/* issue PHY + WRITE command = 0xa into EPCR REG. 0BH */

iow(0x0B, 0x8); /* clear PHY command first */

IOWR(DM9000A_BASE, IO_data, 0x0A); /* issue PHY + WRITE command */

do

{

usleep(STD_DELAY);

}while(0x0a != IORD(DM9000A_BASE,IO_data));

IOWR(DM9000A_BASE, IO_data, 0x08); /* clear PHY command again */

usleep(50); /* wait 1~30 us (>20 us) for PHY + WRITE completion */

}

//-------------------------------------------------------------------------

/* DM9000_init I/O routine */

unsigned int DM9000_init (void) /* initialize DM9000 LAN chip */

{

unsigned int i;

/* software-RESET NIC */

iow(NCR, 0x03); /* NCR REG. 00 RST Bit [0] = 1 reset on, and LBK Bit [2:1] = 01b MAC loopback on */

usleep(20); /* wait > 10us for a software-RESET ok */

iow(NCR, 0x00); /* normalize */

iow(NCR, 0x03);

usleep(20);

iow(NCR, 0x00);

/* set the internal PHY power-on (GPIOs normal settings) */

iow(0x1E, 0x01); /* GPCR REG. 1EH = 1 selected GPIO0 "output" port for internal PHY */

iow(0x1F, 0x01); /* GPR REG. 1FH GEPIO0 Bit [0] = 0 to activate internal PHY */

msleep(5); /* wait > 2 ms for PHY power-up ready */