Linux makefile sample
2014-03-12 10:56
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Anyway, a simple solution that demonstrates simple Makefile concepts would be:
(bear in mind that make requires tab instead of space indentation, so be sure to fix that when copying)
However, to support more C files, you'd have to make new rules for each of them. Thus, to improve:
I tried to make this as simple as possible by omitting variables like $(CC) and $(CFLAGS) that are usually seen in makefiles. If you're interested in figuring that out, I hope I've given you a good start on that.
Here's the Makefile I like to use for C source. Feel free to use it:
It uses the wildcard and patsubst features of the make utility to automatically include .c and .h files in the current directory, meaning when you add new code files to your directory, you won't have to update the Makefile. However, if you want to change the name of the generated executable, libraries, or compiler flags, you can just modify the variables.
In either case, don't use autoconf, please. I'm begging you! :)
Note: a TAB should be in front of every command line.
You can use "cat -etv makefile" to check if there is a TAB, if there is: you can see "^I", otherwise nothing in front of the command line.
HEADERS = program.h headers.h default: program program.o: program.c $(HEADERS) gcc -c program.c -o program.o program: program.o gcc program.o -o program clean:-rm -f program.o -rm -f program
(bear in mind that make requires tab instead of space indentation, so be sure to fix that when copying)
However, to support more C files, you'd have to make new rules for each of them. Thus, to improve:
HEADERS = program.h headers.h OBJECTS = program.o default: program %.o:%.c $(HEADERS) gcc -c $<-o $@ program: $(OBJECTS) gcc $(OBJECTS)-o $@ clean:-rm -f $(OBJECTS)-rm -f program
I tried to make this as simple as possible by omitting variables like $(CC) and $(CFLAGS) that are usually seen in makefiles. If you're interested in figuring that out, I hope I've given you a good start on that.
Here's the Makefile I like to use for C source. Feel free to use it:
TARGET = prog LIBS =-lm CC = gcc CFLAGS =-g -Wall.PHONY:default all clean default: $(TARGET) all:default OBJECTS = $(patsubst %.c,%.o, $(wildcard *.c)) HEADERS = $(wildcard *.h)%.o:%.c $(HEADERS) $(CC) $(CFLAGS)-c $<-o $@ .PRECIOUS: $(TARGET) $(OBJECTS) $(TARGET): $(OBJECTS) $(CC) $(OBJECTS)-Wall $(LIBS)-o $@ clean:-rm -f *.o -rm -f $(TARGET)
It uses the wildcard and patsubst features of the make utility to automatically include .c and .h files in the current directory, meaning when you add new code files to your directory, you won't have to update the Makefile. However, if you want to change the name of the generated executable, libraries, or compiler flags, you can just modify the variables.
In either case, don't use autoconf, please. I'm begging you! :)
Note: a TAB should be in front of every command line.
You can use "cat -etv makefile" to check if there is a TAB, if there is: you can see "^I", otherwise nothing in front of the command line.
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