AT91SAM9260手册关于Power Management Controller章节翻译

       之前都是看别人的文章，现在自己也记录一下自己的心得，公司应用9260好几年了，最近一段时间出现了问题，系统异常重启，老是kernel panic，考虑到底层驱动内核和u-boot一直没动，出现问题的原因应该是电路器件相关的问题。于是，一点点看9260手册，能不能有点蛛丝马迹。之前对时钟这块一直不太懂。这几天狠下心看看到底怎么个意思，之前搞过一次降频，现在再温习一下。

        看到网上没有相关的中文翻译，只是相关的中文数据手册，不慎详细。把自己翻译的关键几处贴上来，以供以后自己留意。。。。。。。。。。。

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1、    能源管理控制器（Power managermentcontroller）

1.1、 
描述

能源管理控制器，简称PMC，通过统配协调控制系统和所有外设时钟操作，已达到优化能源消耗的目的。PMC针对众多外设和ARM处理器进行Enable/Disable的操作。

PMC提供以下几种时钟：

①、MCK,Master Clock,可进行设置操作范围从十几MHZ到设备的最大可操作频率。它主要为各模块提供运转时钟，比如AIC和内存操作单元。

②、PCK,Processor Clock，即处理器时钟，当进入到IDLEMODE时，即空闲模式下，该时钟必须被关闭。

③、外设时钟，典型值与MCK一致，主要作为提供嵌入式外设设备的时钟，例如USART,
SSC, SPI, TWI, TC, MCI等设备，并且可独立控制。为了减少手册中所涉及的时钟名称的数量，外设时钟统一被称为MCK,即the
Peripheral Clocks

1.2、 
MCK controller

The Master Clock Controller providesselection and division of the Master Clock (MCK). MCK is the clock provided toall the peripherals and the memory controller.

MCK控制器主要是作为MCK的分频设置器。MCK是提供给所有外设和内存控制器的基本时钟

The Master Clock is selected from one ofthe clocks provided by the Clock Generator. Selecting the Slow Clock provides aSlow Clock signal to the whole device. Selecting the Main Clock saves powerconsumption of the PLLs.

MCK的时钟源，主要根据下面几个方面的时钟产生。选择低速时钟提供了一个低速信号给整个设备。选择mainclock（即外部晶振 此处18.432MHZ）,作为PLL（锁相环）时钟源。

The Master Clock Controller is made up of aclock selector and a prescaler. It also contains a Master Clock divider whichallows the processor clock to be faster than the Master Clock.

MCK，是由一个时钟选择器和一个预分频器构成。同时，它也包含一个MCK分频器，允许处理器时钟（PCK）比MCK更快。

The Master Clock selection is made bywriting the CSS field (Clock Source Selection) in PMC_MCKR (Master ClockRegister). The prescaler supports the division by a power of 2 of the selectedclock between 1 and 64. The PRES field
in PMC_MCKR programs the prescaler. The MasterClock divider can be programmed through the MDIV field in PMC_MCKR.

MCK时钟的选择是由MCK寄存器PMC_MCKR的CSS位决定的。预分频器支持除以2的幂1到64之间选择的时钟。预分频器由PMC_MCKR寄存器的PRES，可设置相应的数值。MCK分频器的数值通过PMC_MCKR的MDIV来设置。

Each time PMC_MCKR is written to define anew Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until theMaster Clock is established. Then, the MCKRDY bit is set and can trigger aninterrupt to the processor. This feature
is useful when switching from ahigh-speed clock to a lower one to inform the software when the change isactually done.

每一次的PMC_MCKR的数值决定了新的MCK的大小是多小，同时PMC_SR，即状态寄存器的MCKRDY被清零。直至MCK正常运行，否则该MCKRDY的值一直持续为0。然后，MCKRDY被置位，并可以触发处理的中断请求。这个特点，当时钟从高速时钟切换到低速时钟是非常有用的，并通知软件该操作已经被触发。

 

1.3、 
PCK, Processor Clock Controller

The PMC features a Processor ClockController (PCK) that implements the Processor Idle Mode. The Processor Clockcan be disabled by writing the System Clock Disable Register(PMC_SCDR). Thestatus of this clock (at least for debug
purposes) can be read in the System ClockStatus Register (PMC_SCSR).

PMC是使处理器时钟控制器（PCK）执行处理器空闲模式。通过对PMC_SCDR的设置可以对此处理器时钟进行disable操作。该时钟的状态可以通过PMC_SCSR，即系统时钟状态寄存器读取出来。（至少是bubug模式下可以）

The Processor Clock PCK is enabled after areset and is automatically re-enabled by any enabled interrupt. The ProcessorIdle Mode is achieved by disabling the Processor Clock and entering Wait forInterrupt Mode. The Processor
Clock is automatically re-enabled by any enabledfast or normal interrupt, or by the reset of the product.

当进行重启和任何一个使能的中断触发，PCK被使能。通过disable处理器时钟进入到处理器空闲模式，同时进入中断模式下进行等待状态。处理器时钟被重复使能，可以通过以下方式获得，例如可以通过使能快速或者正常的中断，或者重启product。

Note: The ARM Wait for Interrupt mode isentered with CP15 coprocessor operation. Refer to the Atmel application note,Optimizing Power Consumption of AT91SAM9261-based Systems, lit. number 6217.

注意：ARM的中断模式的进入，主要伴随CP15协处理器的操作。可参考ATMEL应用手册，优化能源消耗部分。

When the Processor Clock is disabled, thecurrent instruction is finished before the clock isstopped, but this does notprevent data transfers from other masters of the system bus.

当处理器时钟被失能能，在时钟停止之前，当前的功能操作已经完成，但是，这不能阻止其他主设备的在系统总线上的数据转换。

1.4、 
USB Clock Controller

The USB Source Clock is always generatedfrom the PLL B output. If using the USB, the user must program the PLL togenerate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in CKGR_PLLBR
(see Figure 26-2).

USB的源时钟，是由PLLB的输出决定。如果要使用USB，用户必须设置PLL去产生一个48MHZ、96MHZ和192MHZ信号，精度维持在± 0.25%。时钟的大小依赖于寄存器CKGR_PLLBR的USBDIV的参数设置。

When the PLL B output is stable, i.e., theLOCKB is set:

当PLL B输出恒定，LOCKB应该进行如下设置：

• The USB host clock canbe enabled by setting the UHP bit in PMC_SCER. To save power on this peripheralwhen it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit inPMC_SCSR gives the activity of this clock. The
USB host port require both the12/48 MHz signal and the Master Clock. The Master Clock may be controlled viathe Master Clock Controller.

通过设置PMC_SCER的UHP位，使能USB的主时钟。当该外设未被使用时，为了节约能源，用户可以设置PMC_SCDR的UHP位参数。UHP的位体现了时钟的状态。USB的主设备口要求12/48MHZ的稳定信号和MCK。通过MCK 控制器可以设置MCK的时钟。

1.5、 
Peripheral Clock Controller

The Power Management Controller controlsthe clocks of each embedded peripheral by the way of the Peripheral ClockController. The user can individually enable and disable the Master Clock onthe peripherals by writing into the
Peripheral Clock Enable (PMC_PCER) andPeripheral Clock Disable (PMC_PCDR) registers. The status of the peripheralclock activity can be read in the Peripheral Clock Status Register (PMC_PCSR).

能源管理控制器，通过外设时钟控制器控制着所有外设的时钟。通过设置PMC_PCER（外设时钟使能寄存器）和PMC_PCDR（外设时钟失能寄存器），用户可以独立的去ENABLE和DISABLE着主时钟针对该外设的操作。通过PMC_PCSR，外设时钟状态寄存器，可以读取外设时钟的活动状态。

When a peripheral clock is disabled, theclock is immediately stopped. The peripheral clocks are automatically disabledafter a reset.

当一个外设设备被失能时，该时钟立刻失效。重启之后，外设的时钟也可以自动的失效。

In order to stop a peripheral, it is recommendedthat the system software wait until the peripheral has executed its lastprogrammed operation before disabling the clock. This is to avoid datacorruption or erroneous behavior of
the system.

关闭外设操作，建议按照以下方式去操作，在失能时钟前，软件操作应等待外设完成了所有的应有操作后，才进行关闭外设的操作。这样就避免了系统数据和某种行为的冲突。

The bit number within the Peripheral ClockControl registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the PeripheralIdentifier defined at the product level. Generally, the bit number correspondsto the interrupt source number assigned
to the peripheral

外设时钟控制寄存器，主要是包括PMC_PCER、PMC_PCDR和PMC_PCSR，一般的，每一位的映射到每一个外设。