LDREX 和 STREX

LDREX and STREX

Load and Store Register Exclusive.

LDREX{[code]cond

}

Rt

, [

Rn

{, #

offset

}]
[/code]

STREX{[code]cond

}

Rd

,

Rt

, [

Rn

{, #

offset

}][/code]

where:

cond

is an optional condition code.

Rd

is the destination register for the returned status.

Rt

is the register to load or store.

Rt2

is the second register for doubleword loads or stores.

Rn

is the register on which the memory address is based.

offset

is an optional offset applied to the value in

Rn

.

offset

is
permitted only in 32-bit Thumb instructions. If

offset

is
omitted, an offset of 0 is assumed.

LDREX

loads data from memory.

If the physical address has the Shared TLB attribute,

LDREX

tags the physical address as exclusive access for the current
processor, and clears any exclusive access tag for this processor for any other physical address.

Otherwise, it tags the fact that the executing processor has an outstanding tagged physical address.

STREX

performs a conditional store to memory. The conditions are as follows:

If the physical address does not have the Shared TLB attribute, and the executing processor has an outstanding tagged physical address, the store takes place, the tag is cleared, and the value 0 is returned in

Rd

.

If the physical address does not have the Shared TLB attribute, and the executing processor does not have an outstanding tagged physical address, the store does not take place, and the value 1 is returned in

Rd

.

If the physical address has the Shared TLB attribute, and the physical address is tagged as exclusive access for the executing processor, the store takes place, the tag is cleared, and the value 0 is returned in

Rd

.

If the physical address has the Shared TLB attribute, and the physical address is not tagged as exclusive access for the executing processor, the store does not take place, and the value 1 is returned in

Rd

.

Note

The address used in a

STREX

instruction must be the same as the address in the most
recently executed

LDREX

instruction. The result of executing a

STREX

instruction
to a different address is unpredictable.

ARM

LDREX

and

STREX

are
available in ARMv6 and above.

MOV r1, #0x1                ; load the ‘lock taken’ value
try
LDREX r0, [LockAddr]        ; load the lock value
CMP r0, #0                  ; is the lock free?
STREXEQ r0, r1, [LockAddr]  ; try and claim the lock
CMPEQ r0, #0                ; did this succeed?
BNE try                     ; no - try again
....                        ; yes - we have the lock