并行输入的CRC32校验算法

module crc32  #(parameter N=4)
(
input            rst,     /*async reset,active low*/
input            clk,     /*clock input*/
input     [N*8-1:0] data_in, /*Serial data input pins */
input            d_valid, /* data valid,start to generate CRC, active high*/
output    reg[31:0] crc ,/* start to generate CRC32*/
output    wire[N*8+31:0] data_crc /* start to generate CRC32*/
);

integer i;
reg feedback;
reg [31:0] crc_tmp;
assign data_crc={data_in,crc};
/*
*??sequential process
*/
always @(posedge clk or negedge rst or negedge d_valid)
begin
if(!rst)
crc <= 32'b0;          /*???????????? */
else if(d_valid==1'b0)
crc <= 32'b0;
else
crc <= crc_tmp;
end

/*
*   combination process
*/
always@( data_in or crc)
begin
crc_tmp = crc;
for(i=(N*8-1); i>=0; i=i-1)//32 bit information bit

begin

feedback     = crc_tmp[31] ^ data_in[i];
crc_tmp[31]  = crc_tmp[30]^ feedback;
crc_tmp[30]  = crc_tmp[29];
crc_tmp[29]  = crc_tmp[28];
crc_tmp[28]  = crc_tmp[27];
crc_tmp[27]  = crc_tmp[26];
crc_tmp[26]  = crc_tmp[25]^ feedback;
crc_tmp[25]  = crc_tmp[24];
crc_tmp[24]  = crc_tmp[23];
crc_tmp[23]  = crc_tmp[22]^ feedback;
crc_tmp[22]  = crc_tmp[21]^ feedback;
crc_tmp[21]  = crc_tmp[20];
crc_tmp[20]  = crc_tmp[19];
crc_tmp[19]  = crc_tmp[18];
crc_tmp[18]  = crc_tmp[17];
crc_tmp[17]  = crc_tmp[16];
crc_tmp[16]  = crc_tmp[15]^ feedback;
crc_tmp[15]  = crc_tmp[14];
crc_tmp[14]  = crc_tmp[13];
crc_tmp[13]  = crc_tmp[12];
crc_tmp[12]  = crc_tmp[11]^ feedback;
crc_tmp[11]  = crc_tmp[10]^ feedback ;
crc_tmp[10]  = crc_tmp[9]^ feedback;
crc_tmp[9]   = crc_tmp[8];
crc_tmp[8]   = crc_tmp[7]^ feedback;
crc_tmp[7]   = crc_tmp[6]^ feedback;
crc_tmp[6]   = crc_tmp[5];
crc_tmp[5]   = crc_tmp[4]^ feedback;
crc_tmp[4]   = crc_tmp[3]^ feedback;
crc_tmp[3]   = crc_tmp[2];
crc_tmp[2]   = crc_tmp[1]^ feedback;
crc_tmp[1]   = crc_tmp[0]^ feedback;
crc_tmp[0]   = feedback;
end
end

endmodule

`timescale 1ns/1ns

module crc32_tb #(parameter N=4) ;

reg tb_rst;
reg tb_clk;
reg [N*8-1:0] tb_data_in;
reg tb_d_valid;

wire[N*8+31:0] tb_data_crc;
wire [31:0] tb_crc;

crc32 i1_crc32(
.rst(tb_rst),
.clk(tb_clk),
.data_in(tb_data_in),
.d_valid(tb_d_valid),
.crc(tb_crc),
.data_crc(tb_data_crc)
);

initial
begin
tb_clk=1'b0;
tb_rst=1'b0;
#4  tb_rst=1'b1;
end

initial
begin
tb_d_valid=1'b0;
#5  tb_d_valid =1'b1;
#1  tb_d_valid =1'b0;
#3  tb_d_valid =1'b1;
#1  tb_d_valid =1'b0;
end

initial
begin
tb_data_in=32'h0000;
#4  tb_data_in=32'haaaa;
#4  tb_data_in=32'hffff;
end

always #1 tb_clk <= ~tb_clk;

endmodule

module crc32_decode
#(parameter N=4)(
input            rst,     /*async reset,active low*/
input            clk,     /*clock input*/
input     [N*8+31:0]  data_crc, /*parallel data input pins */
input             d_valid, /* data valid,start to generate CRC, active high*/
output    reg[31:0] crc ,/* start to generate CRC32*/
output    reg is_correct
);

integer i;
reg feedback;
reg [31:0] crc_tmp;
/*
*??sequential process
*/
always @(posedge clk or negedge rst or negedge d_valid)
begin
if(!rst)
crc <= 32'b0;          /*???????????? */
else if(d_valid==1'b0)
crc <= 32'b0;
else
crc <= crc_tmp;
end

/*
*   combination process
*/
always@( data_crc or crc)
begin
crc_tmp = crc;
for(i=N*8+31; i>=0; i=i-1)//32 bit information bit

begin

feedback     = crc_tmp[31] ^ data_crc[i];
crc_tmp[31]  = crc_tmp[30]^ feedback;
crc_tmp[30]  = crc_tmp[29];
crc_tmp[29]  = crc_tmp[28];
crc_tmp[28]  = crc_tmp[27];
crc_tmp[27]  = crc_tmp[26];
crc_tmp[26]  = crc_tmp[25]^ feedback;
crc_tmp[25]  = crc_tmp[24];
crc_tmp[24]  = crc_tmp[23];
crc_tmp[23]  = crc_tmp[22]^ feedback;
crc_tmp[22]  = crc_tmp[21]^ feedback;
crc_tmp[21]  = crc_tmp[20];
crc_tmp[20]  = crc_tmp[19];
crc_tmp[19]  = crc_tmp[18];
crc_tmp[18]  = crc_tmp[17];
crc_tmp[17]  = crc_tmp[16];
crc_tmp[16]  = crc_tmp[15]^ feedback;
crc_tmp[15]  = crc_tmp[14];
crc_tmp[14]  = crc_tmp[13];
crc_tmp[13]  = crc_tmp[12];
crc_tmp[12]  = crc_tmp[11]^ feedback;
crc_tmp[11]  = crc_tmp[10]^ feedback ;
crc_tmp[10]  = crc_tmp[9]^ feedback;
crc_tmp[9]   = crc_tmp[8];
crc_tmp[8]   = crc_tmp[7]^ feedback;
crc_tmp[7]   = crc_tmp[6]^ feedback;
crc_tmp[6]   = crc_tmp[5];
crc_tmp[5]   = crc_tmp[4]^ feedback;
crc_tmp[4]   = crc_tmp[3]^ feedback;
crc_tmp[3]   = crc_tmp[2];
crc_tmp[2]   = crc_tmp[1]^ feedback;
crc_tmp[1]   = crc_tmp[0]^ feedback;
crc_tmp[0]   = feedback;
end

begin
if(crc == 32'h00000000)
is_correct <= 1;
else
is_correct <= 0;
end
end

endmodule

`timescale 1ns/1ns

module crc32_decode_tb #(parameter N=4)  ;

reg tb_rst;

reg tb_clk;

reg [N*8+31:0] tb_data_crc;

reg tb_d_valid;

wire [31:0] tb_crc;

wire tb_is_correct;

crc32_decode i1_crc32_decode(
.rst(tb_rst),
.clk(tb_clk),
.data_crc(tb_data_crc),
.d_valid(tb_d_valid),
.crc(tb_crc),

.is_correct(tb_is_correct)
);

initial

begin

tb_clk=1'b0;

tb_rst=1'b0;

#4  tb_rst=1'b1;

end

initial

begin

tb_d_valid=1'b0;

#5  tb_d_valid =1'b1;

#9  tb_d_valid =1'b0;
#1  tb_d_valid =1'b1;
#9  tb_d_valid =1'b0;

#1  tb_d_valid =1'b1;
#9  tb_d_valid =1'b0;
#1  tb_d_valid =1'b1;
#9  tb_d_valid =1'b0;
#1  tb_d_valid =1'b1;

end

initial
begin

tb_data_crc=64'h0000000000000000;

#4  tb_data_crc=64'h0000aaaab9dfc185;

#10  tb_data_crc=64'h0000aaaab9dfdde1;

#10 tb_data_crc=64'h0000ffff2750af9c;

#10  tb_data_crc=64'h0000ffff27515f67;

#10 tb_data_crc=64'h0000000000000000;

end

always #1 tb_clk <= ~tb_clk;

endmodule