[转]产生任意Duty的PWM波形验证

用MedicalRadiate 3M主板上的FPGA产生500Hz可调PWM;3M板FPGA_CLK由STM32提供的72MHz frequence.

2.pwm.v

`timescale 1ns / 1ps
module pwm(
input clk_72m,
input rst_n,
output reg clk_50k,
output reg pwm_wave        //generator 500Hz pwm
);
reg rst_n1,rst_n2;

parameter       PERIOD = 1440,
PULSEWIDTH = 720,
SIZE =11;    //1440=10110100000,共11位
reg[SIZE-1:0] counter_div;

parameter        DUTY = 40;    //40%

reg [6:0] pwm_counter;

//reg X;
//reg duty;
//////////////////////////////////////////////////////////////////////////////////
//异步复位，同步释放
always@(posedge clk_72m or negedge rst_n)
if(!rst_n)
rst_n1<=1'b0;
else
rst_n1<=1'b1;

always@(posedge clk_72m or negedge rst_n)
if(!rst_n)
rst_n2<=1'b0;
else
rst_n2<=rst_n1;
//////////////////////////////////////////////////////////////////////////////////
//generator 50KHz clock;
always@(posedge clk_72m or negedge rst_n2)
if(!rst_n2)
counter_div<=0;
else if(counter_div<PERIOD-1)
counter_div<=counter_div+1'b1;
else
counter_div<=1'b0;

always@(posedge clk_72m or negedge rst_n2)
if(!rst_n2)
clk_50k<=1'b0;
else if(counter_div<PULSEWIDTH)
clk_50k<=1'b1;
else
clk_50k<=1'b0;
//Modelsim verify ok!
//////////////////////////////////////////////////////////////////////////////////

always@(posedge clk_50k or negedge rst_n2)
begin
if(!rst_n2)
pwm_counter<=1'b0;
else if(pwm_counter==99)
pwm_counter<=1'b0;
else
pwm_counter<=pwm_counter+1'b1;
end

always@(posedge clk_50k or negedge rst_n2)
begin
if(!rst_n2)
pwm_wave <= 1'b0;
else if(pwm_counter==0)
pwm_wave <= 1'b1;
else if(pwm_counter<DUTY)
pwm_wave <= 1'b1;
else
pwm_wave <= 1'b0;
end
//Modelsim verify ok!
endmodule

2.pwm_tb.v

`timescale 1ns / 1ps

module pwm_tb;

// Inputs
reg clk_72m;
reg rst_n;

// Outputs
wire pwm_wave;

// Instantiate the Unit Under Test (UUT)
pwm pwm_tb (
.clk_72m(clk_72m),
.rst_n(rst_n),
.clk_50k(clk_50k),
.pwm_wave(pwm_wave)
);

parameter PERIOD = 14;
initial begin
// Initialize Inputs
clk_72m = 0;
forever
#(PERIOD/2)    clk_72m=~clk_72m;
end

initial begin
rst_n = 0;
#100 rst_n=1;
end

endmodule

4.pwm_ucf.ucf

NET "clk_72m"                LOC = "L22";
NET "rst_n"                    LOC = "G21";
NET "clk_50k"                LOC = "C22";
NET "pwm_wave"         LOC = "C21";
#Created by Constraints Editor (xc3s400-fg456-4) - 2013/05/16
NET "clk_72m" TNM_NET = clk_72m;
TIMESPEC TS_clk_72m = PERIOD "clk_72m" 14 ns HIGH 50%;

NET "clk_72m" CLOCK_DEDICATED_ROUTE = FALSE;

//由于FPGA_CLK没有接专用GCLK上面所以加上述说明语句