有关vhdl的一些问题总结

最近也是刚刚接触VHDL，在用ise开发过程中遇到了一点些小问题，决定记下来。

（1）在生成ip核，将ip核加入到工程，然后通过自己的模块调用ip核，会出现这么一个问题：            

           ERROR:NgdBuild:604- logical block 'myfft' with type 'fft_16' could not be

           resolved. A pin name misspelling can cause this, a missing edif or ngc file,

           case mismatch between the block name and the edif or ngc file name, or the

           misspelling of a type name. Symbol 'fft_16' is not supported in target

           'virtex5'.

解决办法：对Implement design右键选择process properties，然后在translate properties里面有个-sd加入ip核路径：例如我的在G:\ffb_sim\ipcore_dir，加入此路径再编译就没有问题了。

（2）在例化元器件的时候，所有的输入端口必须全接，否则会出现这个错误：

         ERROR:MapLib:978- LUT5 symbol "myfft/blk00000003/blk000008ed" (output

        signal=myfft/blk00000003/sig000009d5) has an equation that uses input pin I1,

        which no longer has a connected signal. Please ensure that all the pins used

        in the equation for this LUT have signals that are not trimmed (see Section 5

       of the Map Report File for details on which signals were trimmed).

（3）在仿真的时候有些位数不对，不会出来结果。例如：fscale_sch : in STD_LOGIC_VECTOR ( 7 downto 0 );

        fscale_sch_proc:process

        begin                                                  --begin掉了也会出不来信号

               fscale_sch<="010101";               --赋值位数少了也不行

               wait;

      end process;

（4）ISE在map的时候出现问题：

       MapLib:701 - Signal ci connected to top level port ci has been removed.

　　Pack:198 - NCD was not produced. All logic was removed from design.  This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'.  You can either add PADs or 'SAVE' attributes to the design, or run
'map -u' to disable logic trimming in the mapper.

可能的原因：当前的模块么有输入和输出，此时，加上一个输入或者输出就可以map通过了

（5）仿真的时候，仿真时间太短，没有得到预期结果；testbench的时候某个变量没有初始化；写testbench没有写wait语句。

（6）生成ip核的时候一定要在ip core generator的窗口下新建一个工程，否则创建失败。