Procedural Timing Control （of Verilog HDL）
2012-11-27 17:03
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http://www.asic-world.com/verilog/timing_ctrl.html
the original above link：http://www.asic-world.com/verilog/timing_ctrl1.html
 | Procedural blocks and timing controls. //过程块和时间性控制 | |
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| Delay controls. //延时控制 Edge-Sensitive Event controls. //边沿触发的时间控制 Level-Sensitive Event controls-Wait statements. 电平触发的时间控制-wait语句 Named Events. //命名事件 | ||
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 | Delay Controls //延迟控制 | |
| Delays the execution of a procedural statement by specific simulation time. 以一个指定仿真时间来延迟过程语句的执行。 | ||
| #< time > < statement >; // 时间延迟的语法格式 | ||
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 | Example - clk_gen //clk_gen时钟产生器 | |
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1 module clk_gen ();
2
3 reg clk, reset;
4
5 initial begin
6 $monitor ("TIME = %g RESET = %b CLOCK = %b", $time, reset, clk);
7 clk = 0;
8 reset = 0;
9 #2 reset = 1;
10 #5 reset = 0;
11 #10 $finish;
12 end
13
14 always
15 #1 clk = ! clk;
16
17 endmodule
You could download file clk_gen.v here | ||
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| Simulation Output | ||
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TIME = 0 RESET = 0 CLOCK = 0 TIME = 1 RESET = 0 CLOCK = 1 TIME = 2 RESET = 1 CLOCK = 0 TIME = 3 RESET = 1 CLOCK = 1 TIME = 4 RESET = 1 CLOCK = 0 TIME = 5 RESET = 1 CLOCK = 1 TIME = 6 RESET = 1 CLOCK = 0 TIME = 7 RESET = 0 CLOCK = 1 TIME = 8 RESET = 0 CLOCK = 0 TIME = 9 RESET = 0 CLOCK = 1 TIME = 10 RESET = 0 CLOCK = 0 TIME = 11 RESET = 0 CLOCK = 1 TIME = 12 RESET = 0 CLOCK = 0 TIME = 13 RESET = 0 CLOCK = 1 TIME = 14 RESET = 0 CLOCK = 0 TIME = 15 RESET = 0 CLOCK = 1 TIME = 16 RESET = 0 CLOCK = 0 | ||
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| Waveform //波形图 | |
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| Edge sensitive Event Controls // 边沿触发的事件控制 | |
| Delays execution of the next statement until the specified transition on a signal. 延迟下一条语句的执行直到一个信号发生了指定的状态变化 | ||
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| syntax : @ (< posedge >|< negedge > signal) < statement >; // 边沿触发的语法格式 | ||
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| Example - Edge Wait //等待边沿的举例 | |
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1 module edge_wait_example();
2
3 reg enable, clk, trigger;
4
5 always @ (posedge enable)
6 begin
7 trigger = 0;
8 // Wait for 5 clock cycles
9 repeat (5) begin
10 @ (posedge clk) ;
11 end
12 trigger = 1;
13 end
14
15 //Testbench code here
16 initial begin
17 $monitor ("TIME : %g CLK : %b ENABLE : %b TRIGGER : %b",
18 $time, clk,enable,trigger);
19 clk = 0;
20 enable = 0;
21 #5 enable = 1;
22 #1 enable = 0;
23 #10 enable = 1;
24 #1 enable = 0;
25 #10 $finish;
26 end
27
28 always
29 #1 clk = ~clk;
30
31 endmodule
You could download file edge_wait_example.v here | ||
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| Simulator Output | ||
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TIME : 0 CLK : 0 ENABLE : 0 TRIGGER : x TIME : 1 CLK : 1 ENABLE : 0 TRIGGER : x TIME : 2 CLK : 0 ENABLE : 0 TRIGGER : x TIME : 3 CLK : 1 ENABLE : 0 TRIGGER : x TIME : 4 CLK : 0 ENABLE : 0 TRIGGER : x TIME : 5 CLK : 1 ENABLE : 1 TRIGGER : 0 TIME : 6 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 7 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 8 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 9 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 10 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 11 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 12 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 13 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 14 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 15 CLK : 1 ENABLE : 0 TRIGGER : 1 TIME : 16 CLK : 0 ENABLE : 1 TRIGGER : 0 TIME : 17 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 18 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 19 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 20 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 21 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 22 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 23 CLK : 1 ENABLE : 0 TRIGGER : 0 TIME : 24 CLK : 0 ENABLE : 0 TRIGGER : 0 TIME : 25 CLK : 1 ENABLE : 0 TRIGGER : 1 TIME : 26 CLK : 0 ENABLE : 0 TRIGGER : 1 | ||
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| Level-Sensitive Event Controls ( Wait statements ) //电平触发的事件控制（wait 语句） | |
| Delays execution of the next statement until < expression > evaluates to true 延迟吓一跳语句的执行，直到<expression>为真时。 | ||
| syntax : wait (< expression >) < statement >; | ||
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| Example - Level Wait // 电平等待 | |
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1 module wait_example();
2
3 reg mem_read, data_ready;
4 reg [7:0] data_bus, data;
5
6 always @ (mem_read or data_bus or data_ready)
7 begin
8 data = 0;
9 while (mem_read == 1'b1) begin
10 // #1 is very important to avoid infinite loop
11 wait (data_ready == 1) #1 data = data_bus;
12 end
13 end
14
15 // Testbench Code here
16 initial begin
17 $monitor ("TIME = %g READ = %b READY = %b DATA = %b",
18 $time, mem_read, data_ready, data);
19 data_bus = 0;
20 mem_read = 0;
21 data_ready = 0;
22 #10 data_bus = 8'hDE;
23 #10 mem_read = 1;
24 #20 data_ready = 1;
25 #1 mem_read = 1;
26 #1 data_ready = 0;
27 #10 data_bus = 8'hAD;
28 #10 mem_read = 1;
29 #20 data_ready = 1;
30 #1 mem_read = 1;
31 #1 data_ready = 0;
32 #10 $finish;
33 end
34
35 endmodule
You could download file wait_example.v here | ||
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| Simulator Output | ||
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TIME = 0 READ = 0 READY = 0 DATA = 00000000 TIME = 20 READ = 1 READY = 0 DATA = 00000000 TIME = 40 READ = 1 READY = 1 DATA = 00000000 TIME = 41 READ = 1 READY = 1 DATA = 11011110 TIME = 42 READ = 1 READY = 0 DATA = 11011110 TIME = 82 READ = 1 READY = 1 DATA = 11011110 TIME = 83 READ = 1 READY = 1 DATA = 10101101 TIME = 84 READ = 1 READY = 0 DATA = 10101101 | ||
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| Intra-Assignment Timing Controls //赋值语句的内部时延控制 | |
| Intra-assignment controls always evaluate the right side expression immediately and assign the result after the delay or event control. 赋值语句的内部时延控制总是立即执行器右侧表达式的值，在时延或者事件控制到达是完成结果的赋值。 | ||
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| In non-intra-assignment controls (delay or event control on the left side), the right side expression is evaluated after the delay or event control. 在非内部时延控制的赋值语句（时延或者事件控制在左侧），在时延或者事件控制之后，执行右侧表达式的计算。 | ||
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| Example - Intra-Assignment //带内部时延赋值语句 | |
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1 module intra_assign();
2
3 reg a, b;
4
5 initial begin
6 $monitor("TIME = %g A = %b B = %b",$time, a , b);
7 a = 1;
8 b = 0;
9 a = #10 0;
10 b = a;
11 #20 $display("TIME = %g A = %b B = %b",$time, a , b);
12 $finish;
13 end
14
15 endmodule
You could download file intra_assign.v here | ||
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| Simulation Output | ||
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TIME = 0 A = 1 B = 0 TIME = 10 A = 0 B = 0 TIME = 30 A = 0 B = 0 | ||
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| Waveform //波形图 | |
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| Modeling Combo Logic with Continuous Assignments // 使用连续赋值语句构建组合逻辑电路 | |
| Whenever any signal changes on the right hand side, the entire right-hand side is re-evaluated and the result is assigned to the left hand side. 无论何时，右侧的任何一个信号发生变化，则整个有右侧将被再次重新计算，并将结果赋值给左侧。 | ||
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| Example - Tri-state Buffer // 三态缓冲器 | |
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1 module tri_buf_using_assign();
2 reg data_in, enable;
3 wire pad;
4
5 assign pad = (enable) ? data_in : 1'bz;
6
7 initial begin
8 $monitor ("TIME = %g ENABLE = %b DATA : %b PAD %b",
9 $time, enable, data_in, pad);
10 #1 enable = 0;
11 #1 data_in = 1;
12 #1 enable = 1;
13 #1 data_in = 0;
14 #1 enable = 0;
15 #1 $finish;
16 end
17
18 endmodule
You could download file tri_buf_using_assign.v here | ||
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| Simulation Output | ||
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TIME = 0 ENABLE = x DATA : x PAD x TIME = 1 ENABLE = 0 DATA : x PAD z TIME = 2 ENABLE = 0 DATA : 1 PAD z TIME = 3 ENABLE = 1 DATA : 1 PAD 1 TIME = 4 ENABLE = 1 DATA : 0 PAD 0 TIME = 5 ENABLE = 0 DATA : 0 PAD z | ||
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| Waveform | |
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| Example - Mux //多路复用器 | |
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1 module mux_using_assign();
2 reg data_in_0, data_in_1;
3 wire data_out;
4 reg sel;
5
6 assign data_out = (sel) ? data_in_1 : data_in_0;
7
8 // Testbench code here
9 initial begin
10 $monitor("TIME = %g SEL = %b DATA0 = %b DATA1 = %b OUT = %b",
11 $time,sel,data_in_0,data_in_1,data_out);
12 data_in_0 = 0;
13 data_in_1 = 0;
14 sel = 0;
15 #10 sel = 1;
16 #10 $finish;
17 end
18
19 // Toggel data_in_0 at #1
20 always
21 #1 data_in_0 = ~data_in_0;
22
23 // Toggel data_in_1 at #2
24 always
25 #2 data_in_1 = ~data_in_1;
26
27 endmodule
You could download file mux_using_assign.v here | ||
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| Simulation Output | ||
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TIME = 0 SEL = 0 DATA0 = 0 DATA1 = 0 OUT = 0 TIME = 1 SEL = 0 DATA0 = 1 DATA1 = 0 OUT = 1 TIME = 2 SEL = 0 DATA0 = 0 DATA1 = 1 OUT = 0 TIME = 3 SEL = 0 DATA0 = 1 DATA1 = 1 OUT = 1 TIME = 4 SEL = 0 DATA0 = 0 DATA1 = 0 OUT = 0 TIME = 5 SEL = 0 DATA0 = 1 DATA1 = 0 OUT = 1 TIME = 6 SEL = 0 DATA0 = 0 DATA1 = 1 OUT = 0 TIME = 7 SEL = 0 DATA0 = 1 DATA1 = 1 OUT = 1 TIME = 8 SEL = 0 DATA0 = 0 DATA1 = 0 OUT = 0 TIME = 9 SEL = 0 DATA0 = 1 DATA1 = 0 OUT = 1 TIME = 10 SEL = 1 DATA0 = 0 DATA1 = 1 OUT = 1 TIME = 11 SEL = 1 DATA0 = 1 DATA1 = 1 OUT = 1 TIME = 12 SEL = 1 DATA0 = 0 DATA1 = 0 OUT = 0 TIME = 13 SEL = 1 DATA0 = 1 DATA1 = 0 OUT = 0 TIME = 14 SEL = 1 DATA0 = 0 DATA1 = 1 OUT = 1 TIME = 15 SEL = 1 DATA0 = 1 DATA1 = 1 OUT = 1 TIME = 16 SEL = 1 DATA0 = 0 DATA1 = 0 OUT = 0 TIME = 17 SEL = 1 DATA0 = 1 DATA1 = 0 OUT = 0 TIME = 18 SEL = 1 DATA0 = 0 DATA1 = 1 OUT = 1 TIME = 19 SEL = 1 DATA0 = 1 DATA1 = 1 OUT = 1 | ||
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| Waveform //波形图 | |
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