User Defined Primitives Part-II (of Verilog HDL)
2012-11-23 15:40
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 | Combinational UDPs //组合逻辑 UDP | |
| In combinational UDPs, the output is determined as a function of the current input. Whenever an input changes value, the UDP is evaluated and one of the state table rows is matched. The output state is set to the value indicated by that row. This is similar to condition statements: each line in table is one condition. 在组合逻辑UDP中，输出是输入的函数，即输出由输入决定。无论何时，当一个输入值发生变化时，UDP进行计算，如果其中的一个状态表的行进行匹配。 输出的状态由匹配的状态行的值指定。这和条件语句相似：真值表中的每一行是一个条件。 | ||
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| Combinational UDPs have one field per input and one field for the output. Input fields and output fields are separated with colon. Each row of the table is terminated by a semicolon. For example, the following state table entry specifies that when the three inputs are all 0, the output is 0. 组合逻辑的udp 的真值表中 每个输入域占一个字段，最后一个域为输出， 输入域，和输出域用：（colon）分隔，每一行用；（semicolon）分号结束。 例如，下面的状态行中指派的当三个输入全为0时，输出为0. | ||
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1 primitive udp_combo (.....); 2 3 table 4 0 0 0 : 0; 5 ... 6 endtable 7 8 endprimitive You could download file udp_combo.v here | ||
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| The order of the inputs in the state table description must correspond to the order of the inputs in the port list in the UDP definition header. It is not related to the order of the input declarations. 状态表中的输入端口的次序必须与udp定义头中的输入端口列表的次序一致（对应），与udp原语内部输入端口的声明次序无关。 | ||
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| Each row in the table defines the output for a particular combination of input states. If all inputs are specified as x, then the output must be specified as x. All combinations that are not explicitly specified result in a default output state of x. 真值表中每一行为一个特殊的输入状态组合定义了一个输出。如果所有的输入指派为x，则输出为也被指派为x。 所有的没有被显示指派的真正表的组合将导致一个不确定的输出 x。 | ||
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 | Example 举例 | |
| In the below example entry, the ? represents a don't-care condition. This symbol indicates iterative substitution of 1, 0, and x. The table entry specifies that when the inputs are 0 and 1, the output is 1 no matter what the value of the current state is. 在下面的例子的行中，？表示不关心的状态。这个？表明其迭代替换值可能是1，0，x中任何一个。 真值表的实体表明如果输入是0和1，则输入出必为1，与其当前的状态无关。 | ||
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| You do not have to explicitly specify every possible input combination. All combinations that are not explicitly specified result in a default output state of x. | ||
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| It is illegal to have the same combination of inputs, specified for different outputs. | ||
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1 // This code shows how UDP body looks like 2 primitive udp_body ( 3 a, // Port a 4 b, // Port b 5 c // Port c 6 ); 7 output a; 8 input b,c; 9 10 // UDP function code here 11 // A = B | C; 12 table 13 // B C : A 14 ? 1 : 1; 15 1 ? : 1; 16 0 0 : 0; 17 endtable 18 19 endprimitive You could download file udp_body.v here | ||
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| TestBench to check above UDP | ||
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1 `include "udp_body.v"
2 module udp_body_tb();
3
4 reg b,c;
5 wire a;
6
7 udp_body udp (a,b,c);
8
9 initial begin
10 $monitor(" B = %b C = %b A = %b",b,c,a);
11 b = 0;
12 c = 0;
13 #1 b = 1;
14 #1 b = 0;
15 #1 c = 1;
16 #1 b = 1'bx;
17 #1 c = 0;
18 #1 b = 1;
19 #1 c = 1'bx;
20 #1 b = 0;
21 #1 $finish;
22 end
23
24 endmodule
You could download file udp_body_tb.v here | ||
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| Simulator Output | ||
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B = 0 C = 0 A = 0 B = 1 C = 0 A = 1 B = 0 C = 0 A = 0 B = 0 C = 1 A = 1 B = x C = 1 A = 1 B = x C = 0 A = x B = 1 C = 0 A = 1 B = 1 C = x A = 1 B = 0 C = x A = x | ||
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the above original link:http://www.asic-world.com/verilog/udp2.html
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