关于FPGA的保持时间不满足

由于FPGA的布线使用的是routing matrix，通常不会出现Hold Violation的情况；如果出现hold violation了，很可能是时钟抖动引起的。

… Hold delay violations are rare in FPGA designs due to the build-in delay of the routing matrix. If a hold violation occurs, it usually indicates a clock skew problem.

关于routing matrix情况描述如下：

An FPGA device contains flexible programmable routing matrix which is used to connect logic blocks with each other. There are various type of connection lines in FPGA:

long lines are used to connect distant logic blocks,

short lines connect neighboring blocks with each other,

dedicated clock trees are used to distribute synchronization signals (these lines have large fanout and little skew and jitter).

dedicated set/reset lines are used to reset all flip-flops in the FPGA.