LPC系列 ARM7 startup.s 启动代码分析（ZZ）

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Mode_USR EQU 0x10

Mode_FIQ EQU 0x11

Mode_IRQ EQU 0x12

Mode_SVC EQU 0x13

Mode_ABT EQU 0x17

Mode_UND EQU 0x1B

Mode_SYS EQU 0x1F ;;定义模式代码

I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled

F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled

;// <h> Stack Configuration (Stack Sizes in Bytes)

;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>

;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>

;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>

;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>

;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>

;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>

;// </h>

UND_Stack_Size EQU 0x00000000

SVC_Stack_Size EQU 0x00000008

ABT_Stack_Size EQU 0x00000000

FIQ_Stack_Size EQU 0x00000000

IRQ_Stack_Size EQU 0x00000080

USR_Stack_Size EQU 0x00000400 ;;各个模式下的堆栈总和

Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \

FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size) ;;总端栈长度

AREA STACK, NOINIT, READWRITE, ALIGN=3 ;;开辟端栈段，定义为可读可写，不初始化内存单元或将内存写0，字节对齐

Stack_Mem SPACE Stack_Size

Stack_Top EQU Stack_Mem + Stack_Size ;;端栈段内容

;// <h> Heap Configuration

;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>

;// </h>

Heap_Size EQU 0x00000000

AREA HEAP, NOINIT, READWRITE, ALIGN=3 ;;开辟一个名为HEAP的段，定义为可写可读，不能初始化内存或使内存为0，字节对齐

Heap_Mem SPACE Heap_Size

; VPBDIV definitions

VPBDIV EQU 0xE01FC100 ; VPBDIV Address

;// <e> VPBDIV Setup

;// <i> Peripheral Bus Clock Rate

;// <o1.0..1> VPBDIV: VPB Clock

;// <0=> VPB Clock = CPU Clock / 4

;// <1=> VPB Clock = CPU Clock

;// <2=> VPB Clock = CPU Clock / 2

;// <o1.4..5> XCLKDIV: XCLK Pin

;// <0=> XCLK Pin = CPU Clock / 4

;// <1=> XCLK Pin = CPU Clock

;// <2=> XCLK Pin = CPU Clock / 2

;// </e>

VPBDIV_SETUP EQU 0 ;;此处定义为是否使VPBDIV初始化

VPBDIV_Val EQU 0x00000000

; Phase Locked Loop (PLL) definitions

PLL_BASE EQU 0xE01FC080 ; PLL Base Address

PLLCON_OFS EQU 0x00 ; PLL Control Offset

PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset

PLLSTAT_OFS EQU 0x08 ; PLL Status Offset

PLLFEED_OFS EQU 0x0C ; PLL Feed Offset

PLLCON_PLLE EQU (1<<0) ; PLL Enable

PLLCON_PLLC EQU (1<<1) ; PLL Connect

PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier

PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider

PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status PLL的一些定义

;// <e> PLL Setup

;// <o1.0..4> MSEL: PLL Multiplier Selection

;// <1-32><#-1>

;// <i> M Value

;// <o1.5..6> PSEL: PLL Divider Selection

;// <0=> 1 <1=> 2 <2=> 4 <3=> 8

;// <i> P Value

;// </e>

PLL_SETUP EQU 1 ;;PLL是否要初始化

PLLCFG_Val EQU 0x00000024

; Memory Accelerator Module (MAM) definitions

MAM_BASE EQU 0xE01FC000 ; MAM Base Address

MAMCR_OFS EQU 0x00 ; MAM Control Offset

MAMTIM_OFS EQU 0x04 ; MAM Timing Offset 内存加速模块定义

;// <e> MAM Setup

;// <o1.0..1> MAM Control

;// <0=> Disabled

;// <1=> Partially Enabled

;// <2=> Fully Enabled

;// <i> Mode

;// <o2.0..2> MAM Timing

;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3

;// <4=> 4 <5=> 5 <6=> 6 <7=> 7

;// <i> Fetch Cycles

;// </e>

MAM_SETUP EQU 1 ;;MAM是否要初始化，1为需要初始化

MAMCR_Val EQU 0x00000002

MAMTIM_Val EQU 0x00000004

; External Memory Controller (EMC) definitions

EMC_BASE EQU 0xFFE00000 ; EMC Base Address

BCFG0_OFS EQU 0x00 ; BCFG0 Offset

BCFG1_OFS EQU 0x04 ; BCFG1 Offset

BCFG2_OFS EQU 0x08 ; BCFG2 Offset

BCFG3_OFS EQU 0x0C ; BCFG3 Offset

;// <e> External Memory Controller (EMC)

EMC_SETUP EQU 0

;// <e> Bank Configuration 0 (BCFG0)

;// <o1.0..3> IDCY: Idle Cycles <0-15>

;// <o1.5..9> WST1: Wait States 1 <0-31>

;// <o1.11..15> WST2: Wait States 2 <0-31>

;// <o1.10> RBLE: Read Byte Lane Enable

;// <o1.26> WP: Write Protect

;// <o1.27> BM: Burst ROM

;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit

;// <2=> 32-bit <3=> Reserved

;// </e>

BCFG0_SETUP EQU 0

BCFG0_Val EQU 0x0000FBEF

;// <e> Bank Configuration 1 (BCFG1)

;// <o1.0..3> IDCY: Idle Cycles <0-15>

;// <o1.5..9> WST1: Wait States 1 <0-31>

;// <o1.11..15> WST2: Wait States 2 <0-31>

;// <o1.10> RBLE: Read Byte Lane Enable

;// <o1.26> WP: Write Protect

;// <o1.27> BM: Burst ROM

;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit

;// <2=> 32-bit <3=> Reserved

;// </e>

BCFG1_SETUP EQU 0

BCFG1_Val EQU 0x0000FBEF

;// <e> Bank Configuration 2 (BCFG2)

;// <o1.0..3> IDCY: Idle Cycles <0-15>

;// <o1.5..9> WST1: Wait States 1 <0-31>

;// <o1.11..15> WST2: Wait States 2 <0-31>

;// <o1.10> RBLE: Read Byte Lane Enable

;// <o1.26> WP: Write Protect

;// <o1.27> BM: Burst ROM

;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit

;// <2=> 32-bit <3=> Reserved

;// </e>

BCFG2_SETUP EQU 0

BCFG2_Val EQU 0x0000FBEF

;// <e> Bank Configuration 3 (BCFG3)

;// <o1.0..3> IDCY: Idle Cycles <0-15>

;// <o1.5..9> WST1: Wait States 1 <0-31>

;// <o1.11..15> WST2: Wait States 2 <0-31>

;// <o1.10> RBLE: Read Byte Lane Enable

;// <o1.26> WP: Write Protect

;// <o1.27> BM: Burst ROM

;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit

;// <2=> 32-bit <3=> Reserved

;// </e>

BCFG3_SETUP EQU 0

BCFG3_Val EQU 0x0000FBEF

;// </e> End of EMC

; External Memory Pins definitions

PINSEL2 EQU 0xE002C014 ; PINSEL2 Address

PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3,

; D0..31, A2..23, JTAG
Pins

PRESERVE8



; Area Definition and Entry Point

; Startup Code must be linked first at Address at which it expects to run.

AREA RESET, CODE, READONLY

ARM

; Exception Vectors

; Mapped to Address 0.

; Absolute addressing mode must be used.

; Dummy Handlers are implemented as infinite loops which can be modified.

Vectors LDR PC, Reset_Addr

LDR PC, Undef_Addr

LDR PC, SWI_Addr

LDR PC, PAbt_Addr

LDR PC, DAbt_Addr

NOP ;
Reserved Vector

LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr

LDR PC, FIQ_Addr

Reset_Addr DCD Reset_Handler ;;定义中断的入口地址

Undef_Addr DCD Undef_Handler

SWI_Addr DCD SWI_Handler

PAbt_Addr DCD PAbt_Handler

DAbt_Addr DCD DAbt_Handler

DCD 0 ; Reserved
Address

IRQ_Addr DCD IRQ_Handler

FIQ_Addr DCD FIQ_Handler

Undef_Handler B Undef_Handler ;;中断处理程序的入口地址

SWI_Handler B SWI_Handler

PAbt_Handler B PAbt_Handler

DAbt_Handler B DAbt_Handler

IRQ_Handler B IRQ_Handler

FIQ_Handler B FIQ_Handler

; Reset Handler

EXPORT Reset_Handler ;;下面是重起时的中断处理函数

Reset_Handler

; Setup External Memory Pins

IF :DEF:EXTERNAL_MODE ;;是否有外部存储模块，有的话则进行初始化

LDR R0, =PINSEL2

LDR R1, =PINSEL2_Val

STR R1, [R0]

ENDIF

; Setup External Memory Controller

IF EMC_SETUP <> 0 ;;若 EMC_SETUP为1，则执行下一个语句

LDR R0, =EMC_BASE

IF BCFG0_SETUP <> 0

LDR R1, =BCFG0_Val

STR R1, [R0, #BCFG0_OFS]

ENDIF

IF BCFG1_SETUP <> 0

LDR R1, =BCFG1_Val

STR R1, [R0, #BCFG1_OFS]

ENDIF

IF BCFG2_SETUP <> 0

LDR R1, =BCFG2_Val

STR R1, [R0, #BCFG2_OFS]

ENDIF

IF BCFG3_SETUP <> 0

LDR R1, =BCFG3_Val

STR R1, [R0, #BCFG3_OFS]

ENDIF

ENDIF ; EMC_SETUP

; Setup VPBDIV 分频

IF VPBDIV_SETUP <> 0

LDR R0, =VPBDIV

LDR R1, =VPBDIV_Val

STR R1, [R0]

ENDIF

; Setup PLL 倍频

IF PLL_SETUP <> 0

LDR R0, =PLL_BASE

MOV R1, #0xAA

MOV R2, #0x55

; Configure and Enable PLL 设置并允许PLL

MOV R3, #PLLCFG_Val

STR R3, [R0, #PLLCFG_OFS]

MOV R3, #PLLCON_PLLE

STR R3, [R0, #PLLCON_OFS]

STR R1, [R0, #PLLFEED_OFS]

STR R2, [R0, #PLLFEED_OFS]

; Wait until PLL Locked

PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]

ANDS R3, R3, #PLLSTAT_PLOCK

BEQ PLL_Loop

; Switch to PLL Clock

MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) ;;语句中的“：OR：” 为相或的意思

STR R3, [R0, #PLLCON_OFS]

STR R1, [R0, #PLLFEED_OFS]

STR R2, [R0, #PLLFEED_OFS]

ENDIF ; PLL_SETUP

; Setup MAM

IF MAM_SETUP <> 0

LDR R0, =MAM_BASE

MOV R1, #MAMTIM_Val

STR R1, [R0, #MAMTIM_OFS]

MOV R1, #MAMCR_Val

STR R1, [R0, #MAMCR_OFS]

ENDIF ; MAM_SETUP

; Memory Mapping (when Interrupt Vectors are in RAM)

MEMMAP EQU 0xE01FC040 ; Memory Mapping Control

IF :DEF:REMAP

LDR R0, =MEMMAP

IF :DEF:EXTMEM_MODE

MOV R1, #3

ELIF :DEF:RAM_MODE

MOV R1, #2

ELSE

MOV R1, #1

ENDIF

STR R1, [R0]

ENDIF

; Initialise Interrupt System

; ...

; Setup Stack for each mode

;;以下函数为进入相应的模式，并定义相应模式的端栈大小

LDR R0, =Stack_Top

; Enter Undefined Instruction Mode and set its Stack Pointer

MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit

MOV SP, R0

SUB R0, R0, #UND_Stack_Size

; Enter Abort Mode and set its Stack Pointer

MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit

MOV SP, R0

SUB R0, R0, #ABT_Stack_Size

; Enter FIQ Mode and set its Stack Pointer

MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit

MOV SP, R0

SUB R0, R0, #FIQ_Stack_Size

; Enter IRQ Mode and set its Stack Pointer

MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit

MOV SP, R0

SUB R0, R0, #IRQ_Stack_Size

; Enter Supervisor Mode and set its Stack Pointer

MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit

MOV SP, R0

SUB R0, R0, #SVC_Stack_Size

; Enter User Mode and set its Stack Pointer

;;最后进入用户模式

MSR CPSR_c, #Mode_USR

MOV SP, R0

SUB SL, SP, #USR_Stack_Size

; Enter the C code

;;进入C语言文件

IMPORT __main

LDR R0, =__main

BX R0

; User Initial Stack & Heap

;;以下编译器处理相关

AREA |.text|, CODE, READONLY

IMPORT __use_two_region_memory

EXPORT __user_initial_stackheap

__user_initial_stackheap

LDR R0, = Heap_Mem

LDR R1, =(Stack_Mem + USR_Stack_Size)

LDR R2, = (Heap_Mem + Heap_Size)

LDR R3, = Stack_Mem

BX LR

END