日报_2012_07_08
2012-07-08 15:45
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XILINX ISE FPGA
module ledloop(iclk,ob);
output[7:0] ob;
input iclk;
reg ob;
reg[24:0] count ;
always@(posedge iclk)
begin
count<=count+1;
ob[7:0]<=count[24:17];
end
endmodule
NET "ob<0>" LOC = P2;
NET "ob<1>" LOC = P3;
NET "ob<2>" LOC = P4;
NET "ob<3>" LOC = P5;
NET "ob<4>" LOC = P14;
NET "ob<5>" LOC = P7;
NET "ob<6>" LOC = P8;
NET "ob<7>" LOC = P15;
NET "iclk" LOC = P54;
MATLAB在图像处理的应用
module ledloop(iclk,ob);
output[7:0] ob;
input iclk;
reg ob;
reg[24:0] count ;
always@(posedge iclk)
begin
count<=count+1;
ob[7:0]<=count[24:17];
end
endmodule
NET "ob<0>" LOC = P2;
NET "ob<1>" LOC = P3;
NET "ob<2>" LOC = P4;
NET "ob<3>" LOC = P5;
NET "ob<4>" LOC = P14;
NET "ob<5>" LOC = P7;
NET "ob<6>" LOC = P8;
NET "ob<7>" LOC = P15;
NET "iclk" LOC = P54;
MATLAB在图像处理的应用
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