vga

module VGA(

RESET,

GCLKP1,

GCLKP2,

R,

G,

B,

VS,

HS

);

input RESET;

input GCLKP1,GCLKP2;

output [3:0]R,G,B;

wire [3:0]R,G,B;

output VS,HS;

wire VS,HS;

//-- SuperVGA timing from NEC monitor manual

//-- Horizontal :

//-- ______________ _____________

//-- | | |

//-- _______________| VIDEO |_______________| VIDEO (next line)

//--

//-- ___________ _____________________ ______________________

//-- |_| |_|

//-- B C <------D-----><-E->

//-- <----------A---------->

//--

//--

//-- Vertical :

//-- ______________ _____________

//-- | | |

//-- _______________| VIDEO |_______________| VIDEO (next frame)

//--

//-- ___________ _____________________ ______________________

//-- |_| |_|

//-- P Q <------R-----><-S->

//-- <----------O---------->

//--

//-- For VESA 800*600 @ 60Hz:

//-- Fh (kHz) :37.88

//-- A (us) :26.4

//-- B (us) :3.2

//-- C (us) :2.2

//-- D (us) :20.0

//-- E (us) :1.0

//--

//-- Fv (Hz) :60.32

//-- O (ms) :16.579

//-- P (ms) :0.106

//-- Q (ms) :0.607

//-- R (ms) :15.84

//-- S (ms) :0.026

//--

//--

//-- Horizonal timing information:

//--

//-- Mode name Pixel sync back active front whole line

//-- clock pulse porch time porch period

//-- (MHz) (us) (pix) (pix) (pix) (pix) (pix)

//--

//-- VGA 800x600 60Hz 40 3.2 128 85 806 37 1056

//--

//-- Vertical timing information:

//-- Mode name Lines line sync back active front whole frame

//-- Total width pulse porch time porch period

//-- (us) (us)(lin) (us)(lin) (us) (lin) (us)(lin) (us) (lin)

//--

//-- VGA 800x600 60Hz 628 26.40 106 4 554 21 15945 604 -1* 16579 628

//------------------------------------------------

//------------------------------------------------

//parameter H_PIXELS = 10'd640; //-- 806

//parameter H_FRONTPORCH = 5'd16; //-- 37

//parameter H_SYNCTIME = 7'd96; //-- 128

//parameter H_BACKPORCH = 6'd48; //-- 85

//parameter H_SYNCSTART = H_PIXELS + H_FRONTPORCH;

//parameter H_SYNCEND = H_SYNCSTART + H_SYNCTIME;

//parameter H_PERIOD = H_SYNCEND + H_BACKPORCH;

//

//parameter V_LINES = 9'd480; //-- 604

//parameter V_FRONTPORCH = 4'd11; //-- -1

//parameter V_SYNCTIME = 2'd2; //-- 4

//parameter V_BACKPORCH = 6'd32; //-- 21

//parameter V_SYNCSTART = V_LINES + V_FRONTPORCH;

//parameter V_SYNCEND = V_SYNCSTART + V_SYNCTIME;

//parameter V_PERIOD = V_SYNCEND + V_BACKPORCH;

parameter H_PIXELS = 640; //-- 806

parameter H_FRONTPORCH = 16; //-- 37

parameter H_SYNCTIME = 96; //-- 128

parameter H_BACKPORCH = 48; //-- 85

parameter H_SYNCSTART = H_PIXELS + H_FRONTPORCH;

parameter H_SYNCEND = H_SYNCSTART + H_SYNCTIME;

parameter H_PERIOD = H_SYNCEND + H_BACKPORCH;

parameter V_LINES = 480; //-- 604

parameter V_FRONTPORCH = 11; //-- -1

parameter V_SYNCTIME = 2; //-- 4

parameter V_BACKPORCH = 32; //-- 21

parameter V_SYNCSTART = V_LINES + V_FRONTPORCH;

parameter V_SYNCEND = V_SYNCSTART + V_SYNCTIME;

parameter V_PERIOD = V_SYNCEND + V_BACKPORCH;

//------------------------------------------------

//------------------------------------------------

reg HsyncB;

reg VsyncB;

reg [9:0]Hcnt;

reg [9:0]Vcnt;

reg Enable;

reg TempR;

reg TempG;

reg TempB;

wire [3:0]ColorR;

wire [3:0]ColorG;

wire [3:0]ColorB;

//--Clock:

//reg [2:0]Count;

wire Period1uS, Period1mS;

reg CLK;

wire CLKTemp ;

//-- Globle Clock Assignment

reg [5:0]Count_clk; //-- 1MHz

reg [9:0]Count1_clk; //-- 1KHz

reg [9:0]Count2_clk; //-- 1Hz

//-- 25 MHz

always@(posedge GCLKP1)

CLK <= ~CLK;

//-----------------------------------------------

//--GCLKP : 50MHz

//--Period: 1uS (Period1uS <= GCLKP1; )

always@(negedge RESET or posedge GCLKP2)

begin

if(!RESET)

Count_clk <= 6'b0;

else if(Count_clk > 6'b110000)

Count_clk <= 6'b0; //-- 1uS

else

Count_clk <= Count_clk + 1'b1;

end

assign Period1uS = Count_clk[5];

//-----------------------------------------------

//--Period: 1mS

always@(negedge RESET or posedge Period1uS)

begin

if(!RESET)

Count1_clk <= 10'b0;

else if(Count1_clk > 10'b1111100110)

Count1_clk <= 10'b0; //-- 1mS

else

Count1_clk <= Count1_clk + 1'b1;

end

assign Period1mS = Count1_clk[9];

//-----------------------------------------------

//--Period: 1S

always@(negedge RESET or posedge Period1mS)

begin

if(!RESET)

Count2_clk <= 10'b0;

else if(Count2_clk > 10'b1111100110)

Count2_clk <= 10'b0; //-- 1S

else

Count2_clk <= Count2_clk + 1'b1;

end

//-- 2 Hz

assign CLKTemp = Count2_clk[8];

//================================================================================================

//-- VGA Clock process

//--------------------------------------------------------------------------------------------------

//-- Horizontal counter

always@(negedge RESET or posedge CLK)

begin

if(!RESET)

Hcnt <= 10'b0;

else if(Hcnt < H_PERIOD)

Hcnt <= Hcnt + 1'b1;

else

Hcnt <= 10'b0;

end

//------------------------------------------------

//-- Vertical counter

always@(negedge RESET or posedge HsyncB)

begin

if(!RESET)

Vcnt <= 10'b0;

else if(Vcnt < V_PERIOD)

Vcnt <= Vcnt + 1'b1;

else

Vcnt <= 10'b0;

end

//------------------------------------------------

//-- Horizontal Sync

//always@(negedge RESET or posedge CLK)

// begin

// if(!RESET)

// HsyncB <= 1'b1;

// else if( Hcnt>=(H_PIXELS + H_FRONTPORCH) && Hcnt<(H_PIXELS + H_FRONTPORCH + H_SYNCTIME) )

// HsyncB <= 1'b0;

// else

// HsyncB <= 1'b1;

// end

always@(negedge RESET or posedge CLK)

begin

if(!RESET)

HsyncB <= 1'b1;

else if( Hcnt>=(H_PIXELS + H_FRONTPORCH) && Hcnt<(H_PIXELS + H_FRONTPORCH + H_SYNCTIME) )

HsyncB <= 1'b0;

else

HsyncB <= 1'b1;

end

//------------------------------------------------

//-- Vertical Sync

always@(negedge RESET or posedge HsyncB)

begin

if(!RESET)

VsyncB <= 1'b1;

else if( (Vcnt >= (V_LINES + V_FRONTPORCH) ) && (Vcnt<(V_LINES + V_FRONTPORCH + V_SYNCTIME) ) )

VsyncB <= 1'b0;

else

VsyncB <= 1'b1;

end

assign HS = HsyncB;

assign VS = VsyncB;

//==============================================

//----------------------------------------------

always@(posedge CLK)

begin

if(!RESET)

Enable <= 1'b0;

else if(Hcnt >= H_PIXELS || Vcnt >= V_LINES)

Enable <= 1'b0;

else

Enable <= 1'b1;

end

//------------------------------------------------

reg [2:0]Count_2;

always@(negedge RESET or posedge CLKTemp)

begin

if(!RESET)

Count_2 <= 3'b0;

else

Count_2 <= Count_2 + 1'b1;

end

//------------------------------------------------

always@(Hcnt[7:5])

begin

case(Hcnt[7:5])

3'b000:

begin

TempR <= 1'b1;

TempG <= 1'b1;

TempB <= 1'b1;

end

3'b001:

begin

TempR <= 1'b0;

TempG <= 1'b0;

TempB <= 1'b0;

end

3'b010:

begin

TempR <= 1'b1;

TempG <= 1'b0;

TempB <= 1'b0;

end

3'b011:

begin

TempR <= 1'b0;

TempG <= 1'b0;

TempB <= 1'b1;

end

3'b100:

begin

TempR <= 1'b0;

TempG <= 1'b1;

TempB <= 1'b0;

end

3'b101:

begin

TempR <= 1'b1;

TempG <= 1'b0;

TempB <= 1'b1;

end

3'b110:

begin

TempR <= 1'b1;

TempG <= 1'b1;

TempB <= 1'b0;

end

3'b111:

begin

TempR <= 1'b1;

TempG <= 1'b1;

TempB <= 1'b1;

end

default:

begin

TempR <= 1'b0;

TempG <= 1'b0;

TempB <= 1'b0;

end

endcase

end

//-------------------------------------------------

assign R = (Enable != 1'b1)? 4'b0:

(TempR == 1'b1)?{Count_2,1'b1}:4'b0;

assign G = (Enable != 1'b1)? 4'b0:

(TempG == 1'b1)?{1'b1,Count_2}:4'b0;

assign B = (Enable != 1'b1)? 4'b0:

(TempB == 1'b1)?{1'b1,Count_2[0],Count_2[1],Count_2[2]}:4'b0;

endmodule