关于STM32 FLASH上运行ecos的内存配置的一点解释

最近很多网友问了关于STM32上运行ecos失败的一些问题，这里简要回答。

1、选择运行方式

cortexm3的ecos，有三种运行方式ram, rom和jtag

ram和jtag是用于调试的，ram方式会把你的执行代码也放到ram中，jtag的代码放在rom中，这个内存模板主要是为了解决jtag连接不上的问题。

rom运行就是我们最后完成项目时候烧入到norflash中运行的方式，代码需要烧入到flash中。

2、完成内存映射

如果你有jlink这样的调试工具，可以直接用rom的方式，调试起来并不复杂。

mlt_cortexm_stm3210e_eval_rom.h

mlt_cortexm_stm3210e_eval_rom.ldi

这两个文件定义了内存布局，下面这个例子是在内部flash中运行的示例文件

// eCos memory layout

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.inc>

MEMORY
{
sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
rom   : ORIGIN = 0x64000000, LENGTH = 0x01000000
ram   : ORIGIN = 0x68000000, LENGTH = 0x00100000
}

SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
SECTION_sram (sram, 0x20000400, FOLLOWING (.got))
SECTION_data (ram, 0x68000000, FOLLOWING (.sram))
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}

hal_vsr_table = 0x20000000;
hal_virtual_vector_table = hal_vsr_table + 128*4;
hal_startup_stack = 0x20000000 + 1024*64;

hal_virtual_vector_table放在内部的sram中，这样有利于中断的快速响应。

3、完成代码中关于内存总线初始化

这部分直观重要，实际上这部分的内容和ecos本身没有关系，是对STM32芯片的外部总线的配置，

设想一下如果你要访问外部的ram，前提当然要设定好响应的芯片引脚和总线读写时序。

__externC void hal_system_init( void )
{
CYG_ADDRESS base;

#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_SRAM)

// Enable peripheral clocks in RCC

base = CYGHWR_HAL_STM32_RCC;

HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHBENR,
CYGHWR_HAL_STM32_RCC_AHBENR_FSMC |
CYGHWR_HAL_STM32_RCC_AHBENR_FLITF|
CYGHWR_HAL_STM32_RCC_AHBENR_SRAM );

HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB2ENR,
CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA |
CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB |
CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC |
CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD |
CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE |
CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF |
CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG);

// Set all unused GPIO lines to input with pull down to prevent
// them floating and annoying any external hardware.

base = CYGHWR_HAL_STM32_GPIOA;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );

base = CYGHWR_HAL_STM32_GPIOB;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );

base = CYGHWR_HAL_STM32_GPIOC;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );

// Set up GPIO lines for external bus

base = CYGHWR_HAL_STM32_GPIOD;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bb44bb );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb );

base = CYGHWR_HAL_STM32_GPIOE;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0xbbbbb4bb );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb );

base = CYGHWR_HAL_STM32_GPIOF;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbb4444 );

base = CYGHWR_HAL_STM32_GPIOG;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x444b4bb4 );

// Set up FSMC NOR/SRAM bank 2 for NOR Flash

base = CYGHWR_HAL_STM32_FSMC;

HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001059 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x10000705 );

// Set up FSMC NOR/SRAM bank 3 for SRAM

HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR3, 0x00001011 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR3, 0x00000200 );

// Set up FSMC NOR/SRAM bank 4 for TFT LCD

HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR4, 0x00001011 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR4, 0x00000201 );

#endif

// Enable flash prefetch buffer and set latency to 2 wait states.
{
cyg_uint32 acr;

base = CYGHWR_HAL_STM32_FLASH;

HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTBE;
acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(2);
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
}
}

整个过程，需要先配置内部总线控制器，配置引脚属性，然后就是对外部RAM时序的配置。

经过了以上几个过程你的外部RAM才能被ecos启用，这个是ecos启动的必要条件。

Set up FSMC NOR/SRAM bank 3 for SRAM