封装好的全局时钟和复位测试模块

//---------   gSignal.v-------------------------

`timescale 1ns/1ns

module gSignal(
gCLK,
gRST_N
);
output reg gCLK;
output reg gRST_N;

parameter    CLK_PERIOD    =    20;
parameter    LO_LEVEL    =    0;
parameter    HI_LEVEL    =    1;

initial    gCLK    =    0;
always
#(CLK_PERIOD/2)    gCLK    =    ~gCLK;

initial    gRST_N    =    1;
task sys_rst_n;
input [31:0]rst_n_time;
begin
gRST_N    =    LO_LEVEL;
#(rst_n_time);
gRST_N    =    HI_LEVEL;
end
endtask

endmodule