PCI-Express 8x

The PCI-Express bus supports 1x, 2x, 4x, 8x [20Gbps], 12x, 16x, and 32x bus widths [transmit / receive pairs]. The PCI-Express [PCIe] 8x signal names and pinout are listed in the table below. The 8x wide PCI Express bus is not used on main-stream PC motherboards.
Links to additional PCI Express pinout widths are listed after the table. Currently the 1x PCIe bus is being used to replace the PCI bus, and the 16x PCIe interface is replacing the AGP expansion slot. The pinout table listed here is defined in the standard.

PCI-Express 8x PinOut

Pin	Side B Connector	Side A Connector
#	Name	Description	Name	Description
1	+12v	+12 volt power	PRSNT#1	Hot plug presence detect
2	+12v	+12 volt power	+12v	+12 volt power
3	RSVD	Reserved	+12v	+12 volt power
4	GND	Ground	GND	Ground
5	SMCLK	SMBus clock	JTAG2	TCK
6	SMDAT	SMBus data	JTAG3	TDI
7	GND	Ground	JTAG4	TDO
8	+3.3v	+3.3 volt power	JTAG5	TMS
9	JTAG1	+TRST#	+3.3v	+3.3 volt power
10	3.3Vaux	3.3v volt power	+3.3v	+3.3 volt power
11	WAKE#	Link Reactivation	PWRGD	Power Good
Mechanical Key
12	RSVD	Reserved	GND	Ground
13	GND	Ground	REFCLK+	Reference Clock Differential pair
14	HSOp(0)	Transmitter Lane 0, Differential pair	REFCLK-
15	HSOn(0)	GND	Ground
16	GND	Ground	HSIp(0)	Receiver Lane 0, Differential pair
17	PRSNT#2	Hotplug detect	HSIn(0)
18	GND	Ground	GND	Ground
19	HSOp(1)	Transmitter Lane 1, Differential pair	RSVD	Reserved
20	HSOn(1)	GND	Ground
21	GND	Ground	HSIp(1)	Receiver Lane 1, Differential pair
22	GND	Ground	HSIn(1)
23	HSOp(2)	Transmitter Lane 2, Differential pair	GND	Ground
24	HSOn(2)	GND	Ground
25	GND	Ground	HSIp(2)	Receiver Lane 2, Differential pair
26	GND	Ground	HSIn(2)
27	HSOp(3)	Transmitter Lane 3, Differential pair	GND	Ground
28	HSOn(3)	GND	Ground
29	GND	Ground	HSIp(3)	Receiver Lane 3, Differential pair
30	RSVD	Reserved	HSIn(3)
31	PRSNT#2	Hot plug detect	GND	Ground
32	GND	Ground	RSVD	Reserved
33	HSOp(4)	Transmitter Lane 4, Differential pair	RSVD	Reserved
34	HSOn(4)	GND	Ground
35	GND	Ground	HSIp(4)	Receiver Lane 4, Differential pair
36	GND	Ground	HSIn(4)
37	HSOp(5)	Transmitter Lane 5, Differential pair	GND	Ground
38	HSOn(5)	GND	Ground
39	GND	Ground	HSIp(5)	Receiver Lane 5, Differential pair
40	GND	Ground	HSIn(5)
41	HSOp(6)	Transmitter Lane 6, Differential pair	GND	Ground
42	HSOn(6)	GND	Ground
43	GND	Ground	HSIp(6)	Receiver Lane 6, Differential pair
44	GND	Ground	HSIn(6)
45	HSOp(7)	Transmitter Lane 7, Differential pair	GND	Ground
46	HSOn(7)	GND	Ground
47	GND	Ground	HSIp(7)	Receiver Lane 7, Differential pair
48	PRSNT#2	Hot plug detect	HSIn(7)
49	GND	Ground	GND	Ground

PCI Express is the new serial bus addition to the PCI series of specifications. This is a serial bus which uses two low-voltage differential LVDS pairs, at 2.5Gb/s in each direction [one transmit pair, and one receive pair]. PCI Express
uses 8B/10B encoding [each 8 bit byte is translated into a 10 bit character in order to equalize the numbers of 1's and 0's sent, and the encoded signal contains an embedded clock]. PCI Express supports 1x [2.5Gbps], 2x, 4x, 8x, 12x, 16x, and 32x
bus widths [transmit / receive pairs]. The PCI-Express [PCIe] 1x signal names and pinout are listed above.

The differential pins [Lanes] listed in the pin out table above are LVDS which stands for: Low Voltage Differential Signaling. The Electrical layer of LVDS listed above is described on the LVDS bus page. The function of the JTAG pins listed
above are described on the JTAG bus page. The function of the SMbus pins listed above are described on the SMbus page.