Signal Integrity Analysis of a Complex Multi-Layered Package



Signal Integrity Analysis of a Complex Multi-Layered Package

As microprocessor clock frequencies increase, and their ASIC power supply voltages decrease to 2.0V and below, the power distribution system of IC packages is becoming an increasingly important design challenge. A number of vias are used both to connect power
planes at multiple locations to each other, and also multiple ground planes to each other. An important design issue is how to determine the number of power and ground planes, and the number and the locations of power and ground vias, for a given power supply
noise margin. The electrical performance of power supply systems has often been characterized by effective inductor models which can be used to estimate power supply noise at low frequencies. For high-end packages, the frequency range of interest is from DC
to a few GHz. Within this frequency range, there can be several package resonant frequencies, and the effective inductor model may become totally invalid.



Figure 1: Structure imported via the CST Cadence Allegro Link

Accurate characterization of power supply systems necessitates electromagnetic field simulations to take into account various electromagnetic interactions in packages. This article investigates the power supply noise in multilayered IC packages. CST MICROWAVE
STUDIO® (CST MWS), based on the Finite Integration technique (FIT), is used for the numerical simulation and the results are validated by means of measurements performed with a VNA. Figure 1 shows the 3D model of the multilayered package which was imported
in CST MWS by using the Cadence® Allegro® link according to workflow process illustrated in Figure 2.



Figure 2: Workflow of the CST Cadence Allegro import

Figure 3 shows the port definitions at the end of the traces i.e. between the top etch board and the top etch via connection for ports 1 and 2 and similarly between the bottom etch board and the bottom etch via connection for ports 3 and 4. In essence, the
port definitions can be regarded as single-ended connections. The input and output ports are numbered as 1 and 3, while ports 2 and 4 are used to measure the coupling to the adjacent line.



Figure 3: Cadence import, trace under investigation and port definition

The goal of the 3D simulation is the evaluation of the S-parameters of a differential line pair coming from top layer to bottom layer by means of through vias. The transient solver is used with a hexahedral mesh implementing CST's FPBA technology. Figure 3
illustrates the 3D simulation results compared to measured results in a frequency range from few MHz to 6 GHz. A good accuracy is achieved over the entire frequency range.



Figure 4: Calculated (green) versus measured (red) S-Parameters

The S-parameters reveal an insertion loss of better than -3 dB at frequencies up to 5.5 GHz, and near-end and far-end crosstalk of greater than -20 dB at frequencies above about 2 GHz. These crosstalk values suggest that a signal integrity analysis of the degradation
of the signal waveforms should be performed. For this purpose CST DESIGN STUDIO™ (CST DS) is used to perform a transient analysis to calculate the eye diagram shown in Figure 5.



Figure 5: CST DS transient simulation setup and resulting eye diagram

Miniaturization and the increasing speed with which signals propagate on digital systems (10-20 Gb/s) make a three dimensional full wave simulation the only possible choice for an accurate and reliable analysis. In this article CST MWS is successfully employed
to simulate and characterize a complex multilayered package model imported using the CST-Allegro link. The comparison of the simulated S-parameters with the measured data shows the accuracy of CST MWS and allows the simulated results to be used with confidence
in other simulation types, for example in circuit level simulations with CST DS.