移植U-Boot-2008.10到友善之臂mini2440（二）
2011-09-23 13:44
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1.2 修改U－Boot中的文件，以同时匹配2440和2410
1.2.1 修改/cpu/arm920t/start.S
(1)删除AT91RM9200使用的LED代码
#include <config.h>
#include <version.h>
//#include <status_led.h> /*这是针对AT91RM9200DK开发板的LED代码，注释掉。*/
......
start_code:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
//bl coloured_LED_init
//bl red_LED_on
(2)修改编译条件支持2440，修改寄存器地址定义
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)|| defined(CONFIG_S3C2440)
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
#define pWTCON 0x15300000
#define INTMSK 0x14400008 /* Interupt-Controller base addresses */
#define CLKDIVN 0x14800014 /* clock divisor register */
#else
#define pWTCON 0x53000000
#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
#define INTSUBMSK 0x4A00001C
#define CLKDIVN 0x4C000014 /* clock divisor register */
#endif
#define CLK_CTL_BASE 0x4C000000
#define MDIV_405 0x7f << 12
#define PSDIV_405 0x21
#define UPLL_MDIV_48 0x38 << 12
#define UPLL_PSDIV_48 0x22
#define MDIV_200 0xa1 << 12
#define PSDIV_200 0x31
(3)修改中断禁止部分
#if defined(CONFIG_S3C2410)
ldr r1, =0x7ff /*根据2410芯片手册，INTSUBMSK有11位可用*/
ldr r0, =INTSUBMSK
str r1, [r0]
#endif
#if defined(CONFIG_S3C2440)
ldr r1, =0x7fff /*根据2440芯片手册，INTSUBMSK有15位可用*/
ldr r0, =INTSUBMSK
str r1, [r0]
#endif
(4)修改时钟设置（2440的主频为405MHz。）
注释掉原来的代码：
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
//ldr r0, =CLKDIVN
//mov r1, #3
//str r1, [r0]
//#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
改为：
# if defined(CONFIG_S3C2440)
/* FCLK:HCLK:PCLK = 1:4:8 */
ldr r0, =CLKDIVN
mov r1, #5
str r1, [r0]
mrc p15, 0, r1, c1, c0, 0 /*read ctrl register */
orr r1, r1, #0xc0000000 /*Asynchronous */
mcr p15, 0, r1, c1, c0, 0 /*write ctrl register */
/*now, CPU clock is 405.00 Mhz */
mov r1, #CLK_CTL_BASE
mov r2, #UPLL_MDIV_48 /*UPLL */
add r2, r2, #UPLL_PSDIV_48
str r2, [r1, #0x08] /*write UPLL first,48MHz */
mov r2, #MDIV_405 /* mpll_405mhz */
add r2, r2, #PSDIV_405 /* mpll_405mhz */
str r2, [r1, #0x04] /* MPLLCON */
#else
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 12 MHz ! 在这里U－Boot有一个错误：以为默认时钟为120MHz。其实如果没有添加以下设置FCLK的语句，芯片内部的PLL是无效的，即FCLK为12MHz。S3C24x0的芯片手册说得很明白。*/
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
mrc p15, 0, r1, c1, c0, 0 /*read ctrl register */
orr r1, r1, #0xc0000000 /*Asynchronous */
mcr p15, 0, r1, c1, c0, 0 /*write ctrl register */
/*now, CPU clock is 202.8 Mhz */
mov r1, #CLK_CTL_BASE
mov r2, #MDIV_200 /* mpll_200mhz */
add r2, r2, #PSDIV_200 /* mpll_200mhz */
str r2, [r1, #0x04]
# endif
#endif /*CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440*/
(5)将从Flash启动改成从NAND Flash启动
在以下U－Boot的设置堆栈语句段(作用是将u-boot的源代码从nor flash到sdram中)：
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot
的前面添加上以下的nand boot代码：
#ifdef CONFIG_S3C2440_NAND_BOOT
@ reset NAND
mov r1, #NAND_CTL_BASE
ldr r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )
str r2, [r1, #oNFCONF]
ldr r2, [r1, #oNFCONF]
ldr r2, =( (1<<4)|(0<<1)|(1<<0) ) @ Active low CE Control
str r2, [r1, #oNFCONT]
ldr r2, [r1, #oNFCONT]
ldr r2, =(0x6) @ RnB Clear
str r2, [r1, #oNFSTAT]
ldr r2, [r1, #oNFSTAT]
mov r2, #0xff @ RESET command
strb r2, [r1, #oNFCMD]
mov r3, #0 @ wait
nand1:
add r3, r3, #0x1
cmp r3, #0xa
blt nand1
nand2:
ldr r2, [r1, #oNFSTAT] @ wait ready
tst r2, #0x4
beq nand2
ldr r2, [r1, #oNFCONT]
orr r2, r2, #0x2 @ Flash Memory Chip Disable
str r2, [r1, #oNFCONT]
@ get read to call C functions (for nand_read())
ldr sp, DW_STACK_START @ setup stack pointer
mov fp, #0 @ no previous frame, so fp=0
@ copy U-Boot to RAM
ldr r0, =TEXT_BASE
mov r1, #0x0
mov r2, #0x30000
bl nand_read_ll
tst r0, #0x0
beq ok_nand_read
bad_nand_read:
loop2:
b loop2 @ infinite loop
ok_nand_read:
@ verify
mov r0, #0
ldr r1, =TEXT_BASE
mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes
go_next:
ldr r3, [r0], #4
ldr r4, [r1], #4
teq r3, r4
bne notmatch
subs r2, r2, #4
beq stack_setup
bne go_next
notmatch:
loop3:
b loop3 @ infinite loop
#endif
#ifdef CONFIG_S3C2410_NAND_BOOT
@ reset NAND
mov r1, #NAND_CTL_BASE
ldr r2, =0xf830 @ initial value
str r2, [r1, #oNFCONF]
ldr r2, [r1, #oNFCONF]
bic r2, r2, #0x800 @ enable chip
str r2, [r1, #oNFCONF]
mov r2, #0xff @ RESET command
strb r2, [r1, #oNFCMD]
mov r3, #0 @ wait
nand1:
add r3, r3, #0x1
cmp r3, #0xa
blt nand1
nand2:
ldr r2, [r1, #oNFSTAT] @ wait ready
tst r2, #0x1
beq nand2
ldr r2, [r1, #oNFCONF]
orr r2, r2, #0x800 @ disable chip
str r2, [r1, #oNFCONF]
@ get read to call C functions (for nand_read())
ldr sp, DW_STACK_START @ setup stack pointer
mov fp, #0 @ no previous frame, so fp=0
@ copy U-Boot to RAM
ldr r0, =TEXT_BASE
mov r1, #0x0 @start address
mov r2, #0x30000 @code size
bl nand_read_ll
tst r0, #0x0
beq ok_nand_read
bad_nand_read:
loop2:
b loop2 @ infinite loop
ok_nand_read:
@ verify
mov r0, #0
ldr r1, =TEXT_BASE
mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes
go_next:
ldr r3, [r0], #4
ldr r4, [r1], #4
teq r3, r4
bne notmatch
subs r2, r2, #4
beq stack_setup
bne go_next
notmatch:
loop3:
b loop3 @ infinite loop
#endif
在“ldr pc, _start_armboot”之前加入：
#if defined(CONFIG_mini2440_LED)
@ LED1 on u-boot stage 1 is ok!
mov r1, #GPIO_CTL_BASE
add r1, r1, #oGPIO_B
ldr r2,=0x155aa
str r2, [r1, #oGPIO_CON]
mov r2, #0xff
str r2, [r1, #oGPIO_UP]
mov r2, #0x1c0
str r2, [r1, #oGPIO_DAT]
#endif
修改目的：如果看到只有LED1亮了，并响起蜂鸣器，说明U－Boot的第一阶段已完成！(针对mini2440，若不是这块开发板的，必须修改或不添加)。
在 “ _start_armboot: .word start_armboot ” 后加入：
.align 2
DW_STACK_START: .word STACK_BASE+STACK_SIZE-4
1.2.1 修改/cpu/arm920t/start.S
(1)删除AT91RM9200使用的LED代码
#include <config.h>
#include <version.h>
//#include <status_led.h> /*这是针对AT91RM9200DK开发板的LED代码，注释掉。*/
......
start_code:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
//bl coloured_LED_init
//bl red_LED_on
(2)修改编译条件支持2440，修改寄存器地址定义
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)|| defined(CONFIG_S3C2440)
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
#define pWTCON 0x15300000
#define INTMSK 0x14400008 /* Interupt-Controller base addresses */
#define CLKDIVN 0x14800014 /* clock divisor register */
#else
#define pWTCON 0x53000000
#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
#define INTSUBMSK 0x4A00001C
#define CLKDIVN 0x4C000014 /* clock divisor register */
#endif
#define CLK_CTL_BASE 0x4C000000
#define MDIV_405 0x7f << 12
#define PSDIV_405 0x21
#define UPLL_MDIV_48 0x38 << 12
#define UPLL_PSDIV_48 0x22
#define MDIV_200 0xa1 << 12
#define PSDIV_200 0x31
(3)修改中断禁止部分
#if defined(CONFIG_S3C2410)
ldr r1, =0x7ff /*根据2410芯片手册，INTSUBMSK有11位可用*/
ldr r0, =INTSUBMSK
str r1, [r0]
#endif
#if defined(CONFIG_S3C2440)
ldr r1, =0x7fff /*根据2440芯片手册，INTSUBMSK有15位可用*/
ldr r0, =INTSUBMSK
str r1, [r0]
#endif
(4)修改时钟设置（2440的主频为405MHz。）
注释掉原来的代码：
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
//ldr r0, =CLKDIVN
//mov r1, #3
//str r1, [r0]
//#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
改为：
# if defined(CONFIG_S3C2440)
/* FCLK:HCLK:PCLK = 1:4:8 */
ldr r0, =CLKDIVN
mov r1, #5
str r1, [r0]
mrc p15, 0, r1, c1, c0, 0 /*read ctrl register */
orr r1, r1, #0xc0000000 /*Asynchronous */
mcr p15, 0, r1, c1, c0, 0 /*write ctrl register */
/*now, CPU clock is 405.00 Mhz */
mov r1, #CLK_CTL_BASE
mov r2, #UPLL_MDIV_48 /*UPLL */
add r2, r2, #UPLL_PSDIV_48
str r2, [r1, #0x08] /*write UPLL first,48MHz */
mov r2, #MDIV_405 /* mpll_405mhz */
add r2, r2, #PSDIV_405 /* mpll_405mhz */
str r2, [r1, #0x04] /* MPLLCON */
#else
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 12 MHz ! 在这里U－Boot有一个错误：以为默认时钟为120MHz。其实如果没有添加以下设置FCLK的语句，芯片内部的PLL是无效的，即FCLK为12MHz。S3C24x0的芯片手册说得很明白。*/
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
mrc p15, 0, r1, c1, c0, 0 /*read ctrl register */
orr r1, r1, #0xc0000000 /*Asynchronous */
mcr p15, 0, r1, c1, c0, 0 /*write ctrl register */
/*now, CPU clock is 202.8 Mhz */
mov r1, #CLK_CTL_BASE
mov r2, #MDIV_200 /* mpll_200mhz */
add r2, r2, #PSDIV_200 /* mpll_200mhz */
str r2, [r1, #0x04]
# endif
#endif /*CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440*/
(5)将从Flash启动改成从NAND Flash启动
在以下U－Boot的设置堆栈语句段(作用是将u-boot的源代码从nor flash到sdram中)：
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot
的前面添加上以下的nand boot代码：
#ifdef CONFIG_S3C2440_NAND_BOOT
@ reset NAND
mov r1, #NAND_CTL_BASE
ldr r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )
str r2, [r1, #oNFCONF]
ldr r2, [r1, #oNFCONF]
ldr r2, =( (1<<4)|(0<<1)|(1<<0) ) @ Active low CE Control
str r2, [r1, #oNFCONT]
ldr r2, [r1, #oNFCONT]
ldr r2, =(0x6) @ RnB Clear
str r2, [r1, #oNFSTAT]
ldr r2, [r1, #oNFSTAT]
mov r2, #0xff @ RESET command
strb r2, [r1, #oNFCMD]
mov r3, #0 @ wait
nand1:
add r3, r3, #0x1
cmp r3, #0xa
blt nand1
nand2:
ldr r2, [r1, #oNFSTAT] @ wait ready
tst r2, #0x4
beq nand2
ldr r2, [r1, #oNFCONT]
orr r2, r2, #0x2 @ Flash Memory Chip Disable
str r2, [r1, #oNFCONT]
@ get read to call C functions (for nand_read())
ldr sp, DW_STACK_START @ setup stack pointer
mov fp, #0 @ no previous frame, so fp=0
@ copy U-Boot to RAM
ldr r0, =TEXT_BASE
mov r1, #0x0
mov r2, #0x30000
bl nand_read_ll
tst r0, #0x0
beq ok_nand_read
bad_nand_read:
loop2:
b loop2 @ infinite loop
ok_nand_read:
@ verify
mov r0, #0
ldr r1, =TEXT_BASE
mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes
go_next:
ldr r3, [r0], #4
ldr r4, [r1], #4
teq r3, r4
bne notmatch
subs r2, r2, #4
beq stack_setup
bne go_next
notmatch:
loop3:
b loop3 @ infinite loop
#endif
#ifdef CONFIG_S3C2410_NAND_BOOT
@ reset NAND
mov r1, #NAND_CTL_BASE
ldr r2, =0xf830 @ initial value
str r2, [r1, #oNFCONF]
ldr r2, [r1, #oNFCONF]
bic r2, r2, #0x800 @ enable chip
str r2, [r1, #oNFCONF]
mov r2, #0xff @ RESET command
strb r2, [r1, #oNFCMD]
mov r3, #0 @ wait
nand1:
add r3, r3, #0x1
cmp r3, #0xa
blt nand1
nand2:
ldr r2, [r1, #oNFSTAT] @ wait ready
tst r2, #0x1
beq nand2
ldr r2, [r1, #oNFCONF]
orr r2, r2, #0x800 @ disable chip
str r2, [r1, #oNFCONF]
@ get read to call C functions (for nand_read())
ldr sp, DW_STACK_START @ setup stack pointer
mov fp, #0 @ no previous frame, so fp=0
@ copy U-Boot to RAM
ldr r0, =TEXT_BASE
mov r1, #0x0 @start address
mov r2, #0x30000 @code size
bl nand_read_ll
tst r0, #0x0
beq ok_nand_read
bad_nand_read:
loop2:
b loop2 @ infinite loop
ok_nand_read:
@ verify
mov r0, #0
ldr r1, =TEXT_BASE
mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes
go_next:
ldr r3, [r0], #4
ldr r4, [r1], #4
teq r3, r4
bne notmatch
subs r2, r2, #4
beq stack_setup
bne go_next
notmatch:
loop3:
b loop3 @ infinite loop
#endif
在“ldr pc, _start_armboot”之前加入：
#if defined(CONFIG_mini2440_LED)
@ LED1 on u-boot stage 1 is ok!
mov r1, #GPIO_CTL_BASE
add r1, r1, #oGPIO_B
ldr r2,=0x155aa
str r2, [r1, #oGPIO_CON]
mov r2, #0xff
str r2, [r1, #oGPIO_UP]
mov r2, #0x1c0
str r2, [r1, #oGPIO_DAT]
#endif
修改目的：如果看到只有LED1亮了，并响起蜂鸣器，说明U－Boot的第一阶段已完成！(针对mini2440，若不是这块开发板的，必须修改或不添加)。
在 “ _start_armboot: .word start_armboot ” 后加入：
.align 2
DW_STACK_START: .word STACK_BASE+STACK_SIZE-4
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