基于VHDL语言编写的多功能数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity dgn_clock is
port(clk1,clk2:in std_logic;
dt:out std_logic_vector (5 downto 0);
q:out std_logic_vector (6 downto 0);
enable:in std_logic;
speak:out std_logic;
m:in std_logic;
mode:in std_logic;
jia:in std_logic);
end dgn_clock;
architecture one of dgn_clock is
signal a,b,c,d,e,f:integer range 0 to 9;
signal t1,t2,t3,t4,t5,tt2,tt4,x,y:std_logic;
signal c1,e1:integer range 0 to 9;
signal c2,d2,e2,f2:integer range 0 to 9;
signal counter,num:integer range 0 to 9;
signal reset,clk1hz:std_logic;
signal mo:integer range 0 to 3;
signal zhishi:std_logic;
signal n1,n2,n3,n4,n5,n6:integer range 0 to 9 ;
signal k:integer range 0 to 1;
signal jishu:integer range 0 to 9999999;
begin
process(clk1)
begin
if clk1'event and clk1='1' then
if jishu=9999999 then
jishu<=0;clk1hz<='1';
else jishu<=jishu+1;clk1hz<='0';
end if;
end if;
end process;
process(mode)
begin
if mode'event and mode='1' then
if mo=3 then mo<=0;
else mo<=mo+1;
end if;
end if;
end process;
process(mo,m,c2,jia)
begin
if jia'event and jia='1' then
if mo=3 and m='0' then
if c2=9 then c2<=0;x<='1';
else c2<=c2+1;x<='0';
end if;
end if;
end if;
end process;
process(d2,x)
begin
if x'event and x='1' then
if d2=5 then d2<=0;
else d2<=d2+1;
end if;
end if;
end process;
process(mo,m,e2,jia)
begin
if jia'event and jia='1' then
if mo=3 and m='1' then
if e2=9 then e2<=0;y<='1';
else e2<=e2+1;y<='0';
end if;
end if;
end if;
end process;
process(f2,y)
begin
if y'event and y='1' then
if f2=2 then f2<=0;
else f2<=f2+1;
end if;
end if;
end process;

process(enable,c,d,e,f)
begin
if enable='1' then
if c2=c and d2=d and e2=e and f2=f then
speak<='1' ;
end if;
elsif enable='0' then speak<='0';
end if;
end process;
process(clk1hz,a,reset)
begin
if clk1hz'event and clk1hz='1' then
if a=9 or reset='1' then a<=0;t1<='1';
else a<=a+1;t1<='0';
end if;
end if;
end process;
process(b,t1,reset)
begin
if t1'event and t1='1' then
if b=5 or reset='1' then b<=0;t2<='1';
else b<=b+1;t2<='0';
end if;
end if;
end process;
process(mo,m,tt2,jia,t2)
begin
if mo=2 and m='0' then tt2<=jia;
else tt2<=t2;
end if;
end process;
process(c,tt2,reset,c1)
begin
if tt2'event and tt2='1' then
if c=9 or reset='1' then c<=0;t3<='1';
else c<=c+1;t3<='0';
end if;
end if;
end process;
process(d,t3,reset)
begin
if t3'event and t3='1' then
if d=5 or reset='1' then d<=0;t4<='1';
else d<=d+1;t4<='0';
end if;
end if;
end process;
process(mo,m,tt4,jia,t4)
begin
if mo=2 and m='1' then tt4<=jia;
else tt4<=t4;
end if;
end process;
process(e,tt4,reset)
begin
if reset='1' then e<=0;
elsif tt4'event and tt4='1' then
if e=9 then e<=0;t5<='1';
else e<=e+1; t5<='0';
end if;
end if;
end process;
process(f,t5,reset)
begin
if reset='1' then f<=0;
elsif t5'event and t5='1' then
f<=f+1;
end if;
end process;
process(mo,m)
begin
if m'event and m='1' then
if mo=1 then
if k=1 then k<=0;
else k<=k+1;
end if;
end if;
end if;
end process;
process(f,e,k)
begin
if k=1 then
if f=2 and e=4 then reset<='1';
else reset<='0';end if;
elsif k=0 then
if f=1 and e=2 then reset<='1';
else reset<='0';end if;
end if;
end process;
process(clk2)
begin
if clk2'event and clk2='1' then
if counter=5 then
counter<=0;
else counter<=counter+1;
end if;
end if ;
end process;
process(mo,k,n1,n2,n3,n4,n5,n6,a,b,c,d,e,f,c2,d2,e2,f2)
begin
if mo=0 then n1<=a;n2<=b;n3<=c;n4<=d;n5<=e;n6<=f;
elsif mo=1 then
if k=0 then n1<=0;n2<=0;n3<=2;n4<=1;n5<=0;n6<=0;
elsif k=1 then n1<=0;n2<=0;n3<=4;n4<=2;n5<=0;n6<=0;
end if;
elsif mo=2 then n1<=0;n2<=0;n3<=c;n4<=d;n5<=e;n6<=f;
elsif mo=3 then n1<=0;n2<=0;n3<=c2;n4<=d2;n5<=e2;n6<=f2;
end if;
end process;
process(counter,n1,n2,n3,n4,n5)
begin
case counter is
when 0=>num<=n1;dt<="000001";
when 1=>num<=n2;dt<="000010";
when 2=>num<=n3;dt<="000100";
when 3=>num<=n4;dt<="001000";
when 4=>num<=n5;dt<="010000";
when 5=>num<=n6;dt<="100000";
when others=>null;
end case;
end process;
process(num)
begin
case num is
when 0=>q<="0111111";
when 1=>q<="0000110";
when 2=>q<="1011011";
when 3=>q<="1001111";
when 4=>q<="1100110";
when 5=>q<="1101101";
when 6=>q<="1111101";
when 7=>q<="0000111";
when 8=>q<="1111111";
when 9=>q<="1101111";
when others=>null;
end case;
end process;
end architecture one;