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6/25/2011 10:56:51 PM

2011-06-26 19:23 323 查看
6/25/2011 10:56:51 PM

HZ 表示1s时钟中断的次数
tick 表示一次时钟中断的时间

pxafb_disable_controller 最后还关闭了LCD的时钟

看看是如果启动的

if (old_state != C_ENABLE) {
fbi->state = C_ENABLE;
pxafb_setup_gpio(fbi);
pxafb_enable_controller(fbi);
__pxafb_lcd_power(fbi, 1);
#ifdef CONFIG_LITTLETON_SMART_PANEL
wake_up_interruptible(&screen_update_wait_q);
#endif
__pxafb_backlight_power(fbi, 1);
if(fbi->set_overlay_ctrlr_state)
fbi->set_overlay_ctrlr_state(fbi, C_ENABLE);
}

pxafb_setup_gpio

开始映射内存了

pxafb_map_video_memory

fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + 4 * PAGE_SIZE);

预留了4个page

Write combining (WC)[1] is a computer bus technique for allowing data to be combined and temporarily stored in a buffer -- the write combine buffer (WCB) -- to be released together later in burst mode instead of writing (immediately) as single bits or small chunks.

Write combining cannot be used for general memory access (data or code regions) due to the 'weak ordering'. Write-combining does not guarantee that the combination of writes and reads is done in the correct order. For example, a Write/Read/Write combination to a specific address would lead to the write combining order of Read/Write/Write which can lead to obtaining wrong values with the first read (which potentially relies on the write before).

In order to avoid the problem of read/write order described above, the write buffer can be treated as a fully-associative cache and added into the memory hierarchy of the device in which it is implemented[2]. Adding complexity slows down the memory hierarchy so this technique is often only used for memory which does not need 'strong ordering' (always correct) like the frame buffers of video cards.

struct page {
unsigned long flags; /* Atomic flags, some possibly
* updated asynchronously */
atomic_t _count; /* Usage count, see below. */
atomic_t _mapcount; /* Count of ptes mapped in mms,
* to show when page is mapped
* & limit reverse map searches.
*/
union {
struct {
unsigned long private; /* Mapping-private opaque data:
* usually used for buffer_heads
* if PagePrivate set; used for
* swp_entry_t if PageSwapCache;
* indicates order in the buddy
* system if PG_buddy is set.
*/
struct address_space *mapping; /* If low bit clear, points to
* inode address_space, or NULL.
* If page mapped as anonymous
* memory, low bit is set, and
* it points to anon_vma object:
* see PAGE_MAPPING_ANON below.
*/
};
#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
spinlock_t ptl;
#endif
};
pgoff_t index; /* Our offset within mapping. */
struct list_head lru; /* Pageout list, eg. active_list
* protected by zone->lru_lock !
*/
/*
* On machines where all RAM is mapped into kernel address space,
* we can simply calculate the virtual address. On machines with
* highmem some memory is mapped into kernel virtual memory
* dynamically, so we need a place to store that address.
* Note that this field could be 16 bits on x86 ... ;)
*
* Architectures with slow multiplication can define
* WANT_PAGE_VIRTUAL in asm/page.h
*/
#if defined(WANT_PAGE_VIRTUAL)
void *virtual; /* Kernel virtual address (NULL if
not kmapped, ie. highmem) */
#endif /* WANT_PAGE_VIRTUAL */
};

用来描述一个物理页

struct vm_region {
struct list_head vm_list;
unsigned long vm_start;
unsigned long vm_end;
struct page *vm_pages;
int vm_active;
};

arm 中用来描述一块虚拟地址空间

#define CONSISTENT_DMA_SIZE SZ_8M

定义了8M的DMA区域

#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)

/*
* These are the page tables (2MB each) covering uncached, DMA consistent allocations
*/
static pte_t *consistent_pte[NUM_CONSISTENT_PTES];

每个页表项就是2M

也就是说8M的DMA区域可以分成4个不同的页表项

要分配也是在这4个页表项中进行分配

如果第一个pte就是null,就返回失败

if (!consistent_pte[0]) {
printk(KERN_ERR "%s: not initialised/n", __func__);
dump_stack();
return NULL;
}

u64 *dma_mask; /* dma mask (if dma'able device) */
u64 coherent_dma_mask;/* Like dma_mask, but for
alloc_coherent mappings as
not all hardware supports
64 bit addresses for consistent
allocations such descriptors. */

DMA掩码

一致性DMA掩码

AMBA(Advanced Microcontroller Bus Architecture)总线规范是ARM公司设计的一种用于高性能嵌入式系统的总线标准。它独立于处理器和制造工艺技术,增强了各种应用中的外设和系统宏单元的可重用性。AMBA总线规范是一个开放标准,可免费从ARM获得。目前,AMBA 拥有众多第三方支持,被ARM公司90%以上的合作伙伴采用,在基于ARM处理器内核的SoC设计中,已经成为广泛支持的现有互联标准之一。AMBA总线规范2.0于1999年发布,该规范引入的先进高性能总线(AHB)是现阶段AMBA实现的主要形式。AHB的关键是对接口和互连均进行定义,目的是在任何工艺条件下实现接口和互连的最大带宽。AHB接口已与互连功能分离,不再仅仅是一种总线,而是一种带有接口模块的互连体系。

  AMBA总线规范主要设计目的如下:① 满足具有一个或多个CPU或DSP的嵌入式系统产品的快速开发要求;② 增加设计技术上的独立性,确保可重用的多种IP核可以成功地移植到不同的系统中,适合全定制、标准单元和门阵列等技术;③ 促进系统模块化设计,以增加处理器的独立性;④ 减少对底层硅的需求,以使片外的操作和测试通信更加有效。

  AMBA总线是一个多总线系统。规范定义了三种可以组合使用的不同类型的总线:AHB(Advanced High-performance Bus)、ASB(Advanced System Bus)和APB(Advanced Peripheral Bus)

AMBA 高级微控总线协议
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