Intel manual appendix a 说明intel可以监控到的事件

APPENDIX A
PERFORMANCE-MONITORING EVENTS
This appendix lists the performance-monitoring events that can be monitored with
the Intel 64 or IA-32 processors. The ability to monitor performance events and the
events that can be monitored in these processors are mostly model-specific, except
for architectural performance events, described in Section A.1.
Non-architectural performance events (i.e. model-specific events) are listed for each
generation of microarchitecture:
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Section A.2 - Processors based on Intel® microarchitecture codename Nehalem
Section A.4 - Processors based on Enhanced Intel® CoreTM microarchitecture
Section A.5 - Processors based on Intel® CoreTM microarchitecture
Section A.6 - Processors based on Intel® AtomTM microarchitecture
Section A.7 - Intel® CoreTM Solo and Intel® CoreTM Duo processors
Section A.8 - Processors based on Intel NetBurst® microarchitecture
Section A.9 - Pentium® M family processors
Section A.10 - P6 family processors
Section A.11 - Pentium® processors
NOTE
These performance-monitoring events are intended to be used as
guides for performance tuning. The counter values reported by the
performance-monitoring events are approximate and believed to be
useful as relative guides for tuning software. Known discrepancies
are documented where applicable.
A.1
ARCHITECTURAL PERFORMANCE-MONITORING
EVENTS
Architectural performance events are introduced in Intel Core Solo and Intel Core
Duo processors. They are also supported on processors based on Intel Core microar-
chitecture. Table A-1 lists pre-defined architectural performance events that can be
configured using general-purpose performance counters and associated event-select
registers.
Vol. 3 A-1
PERFORMANCE-MONITORING EVENTS
Table A-1. Architectural Performance Events
Event Event Mask Mnemonic
Num.
Umask
Value
3CH UnHalted Core Cycles 00H Unhalted core cycles
3CH UnHalted Reference 01H Unhalted reference cycles
Cycles
Description
C0H Instruction Retired 00H LLC Reference 4FH LL cache references
2EH LLC Misses 41H LL cache misses
C4H Branch Instruction Retired 00H Branch instruction retired
C5H Branch Misses Retired
Measures
bus cycle1
Instruction retired
2EH
Comment
Mispredicted Branch Instruction retired
00H
NOTES:
1. Implementation of this event in Intel Core 2 processor family, Intel Core Duo, and Intel Core Solo pro-
cessors measures bus clocks.