总线架构性能评估--ARM的解决之道
2010-06-28 15:53
148 查看
ARM is offering one answer: an IP block that can be inserted into the RTL or transaction-level model of a design and used during software simulation or hardware emulation to collect statistics on dataflows. This data is far more compact than actual recordings or vector lists. The block can then be used to generate pseudorandom traffic streams based on the statistics.
Using this verification IP, designers can set up their simulation model of the chip for suspected traffic-corner cases. They can then use the traffic-analysis IP blocks to profile the traffic flowing between blocks in the simulation during runs. The statistical profiles can then be used, at either the transaction or cycle-accurate level and apparently also with RTL, to examine the operation of the chip over a range of interconnect scales, topologies, buffer sizes, and the like.
In effect, the IP blocks allow designers to apply traditional functional verification techniques of pseudorandom vector testing not merely to the logical correctness of the interconnect, but also to its dynamic performance. It is an important step in dealing with the emergence of on-chip buses and links as a critical feature in complex SOCs.
Using this verification IP, designers can set up their simulation model of the chip for suspected traffic-corner cases. They can then use the traffic-analysis IP blocks to profile the traffic flowing between blocks in the simulation during runs. The statistical profiles can then be used, at either the transaction or cycle-accurate level and apparently also with RTL, to examine the operation of the chip over a range of interconnect scales, topologies, buffer sizes, and the like.
In effect, the IP blocks allow designers to apply traditional functional verification techniques of pseudorandom vector testing not merely to the logical correctness of the interconnect, but also to its dynamic performance. It is an important step in dealing with the emergence of on-chip buses and links as a critical feature in complex SOCs.
相关文章推荐
- 评估性能时常见错误和解决方法
- Genymotion 安装arm-v7架构app的问题解决
- Web应用架构演进及系统性能、稳定性所需要解决的问题
- ARM架构+网络解决方法。
- Cocos2d-x第三方类库不支持arm64的问题解决(64位架构)
- Cocos2d-x第三方类库不支持arm64的问题解决(64位架构)
- zynq-7000系列基于zynq-zed双核ARM-Cortex-A9性能的评估测试(多核的使用)
- Cocos2d-x(或者应用)第三方类库不支持arm64的有关问题解决(64位架构)
- 安装Sqlserver2005出现"性能监视器计数器要求"错误解决方法
- 〖Android〗arm-linux-androideabi-gdb报 libpython2.6.so.1.0: cannot open shared object file错误的解决方法
- 写注册表永久保存之后,系统性能变慢的解决!
- 架构中的技术性解决难题
- ARM全新旗舰架构!Cortex-A72正式发布
- 网站性能优化 - 数据库及服务器架构篇
- Android音频架构性能分析
- 关于在arm裸板编程时使用printf问题的解决方法
- 在Ubuntu系统下arm-none-linux-gnueabi-gcc: not found 的解决办法
- 从LiveJournal后台发展看 大型网站系统架构以及性能优化方法(转)