AutoESL at DAC 2010: High-level Synthesis for ASICs and FPGAs

Presentations
by Atrenta, IMEC, National Instruments, Qualcomm, and Xilinx as well as
participation in a panel on best choice of input language for HLS

CUPERTINO, California – June 7, 2010
– AutoESL Design Technologies, the technology leader in high-level synthesis (HLS), will exhibit and demonstrate their AutoPilot ASIC™

and
AutoPilot FPGA™

solutions in Booth # 1577 at

DAC 2010

in Anaheim, California on June 14-16, 2010.
There
will be presentations in the booth by Atrenta, IMEC, National
Instruments, Qualcomm, and Xilinx. In addition, AutoESL will
participate in a panel on What Input Language is the Best Choice for High-Level Synthesis (HLS)?

Activities in Booth #1577:

·

Exhibition and demonstrations of AutoPilot ASIC and AutoPilot FPGA

·

High Performance DSP Design Using High-Level Synthesis

– presentation by Xilinx

on

Mon, June 14 and Wed, June 16, 2010 at 1pm

·

Graphical FPGA Design for Advanced Control and Robotics

– presentation by National Instruments

on Tue, June 15, 2010 at 1pm

·

A Peek into the Future – A Working 3D Design Flow

— presentation and demonstration by Atrenta, IMEC,

Qualcomm,

and AutoESL on Tue, June 15 at 2pm and Wed, June 16, 2010 at 11am

To sign up for a private demonstration or meeting, please register at
http://www.autoesl.com/dac.php
Panel:

Devadas Varma, PhD, chief operating officer at AutoESL will participate in a panel entitled What Input Language is the Best Choice for High-Level Synthesis (HLS)?

in
Room 207AB on Thursday, June 17, 2010 from 4:30pm – 6pm. In 2009,
tape-outs for SoCs containing intellectual property (IP) developed with
HLS exceeded 50 for the first time. Now that the practicality and value
of HLS is established, engineers are asking the question: “What input
language works best?” Chaired by Dan Gajski of the Univ. of California,
Irvine, panelists explain why the answer to this question is critical,
since it drives key decisions regarding the tool/methodology
infrastructure companies will create around this new flow. ANSI-C/C++
advocates cite ease-of-learning and simulation speed. SystemC advocates
make similar claims, and point to SystemC’s hardware-oriented features.
Proponents of BSV (Bluespec SystemVerilog) claim that the language
enhances architectural transparency and control. To realize the full
benefits of HLS, companies must consider all of these factors. For full
panel information, see
http://www2.dac.com/panels.aspx?event=38&topic=10
About AutoESL Design Technologies

AutoESL delivers the industry’s leading high-level
synthesis (HLS) solution targeting ASICs and FPGAs. AutoESL provides an
easy to adopt & easy to deploy HLS solution offering the industry’s
only unified language support of C, C++ and System C for system
designers for both ASIC and FPGA designs, and that produces results
which are optimized for area, performance and power, resulting in the
highest-quality implementation-aware RTL.
AutoESL’s
products address various markets including DSP, Video, Networking,
Wireless and High-Performance Computing. AutoESL is headquartered in
Cupertino, CA with offices in China, Europe, Los Angeles and Texas. www.autoesl.com

Keywords

3D Design Flow
, AutoESL
, AutoPilot ASIC
, AutoPilot FPGA
, DAC 2010
, DAC 47
, Devadas Varma
, High Level Synthesis