Verilog语言——序列检测器

设计一个序列检测器，检测器在有“101”序列输入时输出为1，其他输入情况下，输出为0。

module xuliejiance(x,z,clk,rst,state);

input x,clk,rst;

output z;
output[2:0] state;
reg[2:0] state;
wire z;
parameter IDLE='d0,A='d1,B='d2,C='d3,G='D4;
assign z=(state==C&&x==1)?1:0;
always @(posedge clk)
if(!rst)
begin
state <= IDLE;
end
else
casex(state)
IDLE : if(x==1)
begin
state <= A;
end
A: if(x==0)
begin
state <= B;
end
B: if(x==1)
begin
state <= C;
end
else
begin
state <= G;
end
C: if(x==1)
begin
state <= A;
end
else
begin
state <= G;
end
G: if(x==1)
begin
state <= A;
end
default:state=IDLE; //缺省状态为初始状态。
endcase
endmodule