xilinx 网站应用笔记 3 _3rdparty

File Archive: app_3rdparty

Contents of /pub/applications/3rdparty
Applications Relating to Third Party interfaces

=============================================================================
Filename                Size             File Description
=============================================================================

cr225634.zip
17 Kb  Uploaded: 06-18-2006
Patch for CR225634 netgen unable to connect the
power and GND lines in the netlist
For Win XP
Category: SW Update, FPGA Imp tools
cr230757_lin.zip
17916 Kb  Uploaded: 05-29-2006
Linux Version of Patched GT11 smartmodel as per
cr230757 to fix the problem where the smartmodel
was not working correctly
For RHEL 32bit WS 3.0
Category: SW Update, Third Party
cr230757_nt.zip
15953 Kb  Uploaded: 05-29-2006
PC Version of Patched GT11 smartmodel as per
cr230757 to fix the problem where the smartmodel
was not working correctly
For Win XP
cr230757_sol.zip
25246 Kb  Uploaded: 05-29-2006
Solaris Version of Patched GT11 smartmodel as
per cr230757 to fix the problem where the
smartmodel was not working correctly
For Solaris 2.9
cr344587.zip
226 Kb  Uploaded: 09-18-2006
Patch for CR344587 on netgen to use X_ODDR
instead of 3 X_FFs for tristate path.
For Win XP
Category: SW Update, FPGA Imp tools
lab08_web.zip
8600 Kb  Uploaded: 01-15-2003
This Zip file contains the popular Web server
demo on the V2Pro platform . The design file is
the Lab 08 on the EDK page, however, using C.13
build.
For All Platforms
SW Release: F5.1i
m1_hdl_src.tar.Z        107 Kb  VHDL and Verilog Example files to accompany the
Xilinx Synthesis and Simulation Design Guide
(for M1). Source code-only.
For All Platforms
Uploaded: 01-20-98
m1_hdl_src.zip          126 Kb  VHDL and Verilog Example files to accompany the
Xilinx Synthesis and Simulation Design Guide
(for M1). Source code-only.
For All Platforms
Uploaded: 01-20-98
m1_verilog.src.zip       62 Kb  Verilog example files to accompany the Xilinx
Synthesis and Simulation Design Guide (for M1).
Source code-only.
For All Platforms
Uploaded: 01-20-98
m1_verilog_src.tar.Z     55 Kb  Verilog example files to accompany the Xilinx
Synthesis and Simulation Design Guide (for M1).
Source code-only.
For All Platforms
Uploaded: 01-20-98
m1_vhdl_src.tar.Z        58 Kb  VHDL example files to accompany the Xilinx
Synthesis and Simulation Design Guide (for M1).
Source code-only.
For All Platforms
Uploaded: 01-20-98
m1_vhdl_src.zip          66 Kb  VHDL example files to accompany the Xilinx
Synthesis and Simulation Design Guide (for M1).
Source code-only.
For All Platforms
Uploaded: 01-20-98
m1_xsi_hdl.tar.Z      11223 Kb  Verilog and VHDL example files to accompany the
Synopsys (XSI) Synthesis and Simulation Design
Guide (for M1). Source, script and all design
files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_hdl.zip         7683 Kb  Verilog and VHDL example files to accompany the
Synopsys (XSI) Synthesis and Simulation Design
Guide (for M1). Source, script and all design
files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_verilog.tar.Z   5128 Kb  Verilog example files to accompany the Synopsys
(XSI) Synthesis and Simulation Design Guide (for
M1). Source, script and all design files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_verilog.zip     3545 Kb  Verilog example files to accompany the Synopsys
(XSI) Synthesis and Simulation Design Guide (for
M1). Source, script and all design files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_vhdl.tar.Z      6181 Kb  VHDL example files to accompany the Synopsys
(XSI) Synthesis and Simulation Design Guide (for
M1). Source, script and all design files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_vhdl.zip        4169 Kb  VHDL example files to accompany the Synopsys
(XSI) Synthesis and Simulation Design Guide (for
M1). Source, script and all design files.
For All Platforms
Uploaded: 01-20-98
mxe6.1e_8.2sp1_simulation_libraries.zip
29407 Kb  Uploaded: 06-29-2006
Modelsim Xilinx Edition III 6.1e Library update
8.1sp2 Libraries updated 6-29-06
For Win XP
Category: SW Update, Libraries
mxe6.1e_8.2sp2_simulation_libraries.zip
30729 Kb  Uploaded: 08-21-2006
ModelSim Xilinx Edition III 6.1E Library Update
8.2i SP2 Libraries Updated 8-21-06
For Win XP
Category: SW Update, Libraries
mxe6.1e_8.2sp3_simulation_libraries.zip
29757 Kb  Uploaded: 09-18-2006
mxe6.1e_8.2sp3_simulation_libraries.zip contains
Modelsim V6.1e precompiled libraries for ISE
8.2sp3.
For Win XP
Category: SW Update, Libraries
mxe6.1e_82i_ip1_xilinxcorelib.zip
48802 Kb  Uploaded: 07-24-2006
MXE library update for MXE 6.1e Ip update 1.
INSTRUCTIONS FOR INSTALLING THE LIBRARIES 1)
Download the zip file into a temporary
directory. 2) Unzip the file to the MODELSIM
install directory, eg: C:/Modeltech_XE/
For Win XP
Category: SW Update, Libraries
mxe6.1e_82i_ip2_xilinxcorelib.zip
51227 Kb  Uploaded: 10-03-2006
Libraries for Modelsim XE 6.1e for ISE 8.2iSP3
IP update 2. Release date : 10/03/2006
For Win XP
Category: SW Update, Third Party
mxe6.1e_82i_ip3_xilinxcorelib.zip
51518 Kb  Uploaded: 01-04-2007
INSTRUCTIONS FOR INSTALLING THE LIBRARIES 1)
Download the zip file into a temporary
directory. 2) Unzip the file to the MODELSIM
install directory, eg: C:/Modeltech_XE/
For Win XP
Category: SW Update, Libraries
solution14147.zip
3584 Kb  Uploaded: 03-28-2002
.zip file with .dll files and readme.txt. to be
linked from solution 14147.
Solution #: 14147
For Win NT 4.0
SW Release: F4.1i
Category: SW Update, Third Party
tlb_errata.patch.zip
2 Kb  Uploaded: 08-01-2003
For embedded Linux a patch is available that
works around the errata. The patch applies
cleanly against the MontaVista Professional
Linux 3.0 kernel for ML300.
Solution #: 14052
For All Unix
Category: SW Update, Other
vstbsim.zip             191 Kb  App note and sample design files describing
Board-level simulation with OrCAD VST v1.20
For All Windows
Uploaded: 12-04-97
xilinx_verdi_symbols.tar.gz
19562 Kb  Uploaded: 03-04-2005
This is the symbol libraries to be used with the
Novas Verdi / Debussy debugging environment
For All Platforms