(筆記) 如何以絕對時間指定testbench波形? (SOC) (Verilog)

Abstract
一般指定testbench波形，用的是相對時間，若想用絕對時間呢?

Introduction
一般指定testbench波形，用的是相對時間，如下所是：(此範例原為(筆記) 如何設計邊緣檢測電路? (SOC) (Verilog)的testbench)

1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com 3
4 Filename : posedge_detection_tb.v
5 Compiler : ModelSim-Altera 6.1g
6 Description : testbench of posedge_detection.v
7 Release : 07/09/2008 1.0
8 */
9
10 `timescale 1ns/10ps
11 module posedge_detection_tb;
12
13 reg clk;
14 reg rst_n;
15 reg i_data_in;
16 wire o_rising_edge;
17
18 posedge_detection u0 (
19 .clk(clk),
20 .rst_n(rst_n),
21 .i_data_in(i_data_in),
22 .o_rising_edge(o_rising_edge)
23 );
24
25 parameter clkper = 100;
26 initial begin
27 clk = 1'b0;
28 end
29
30 always begin
31 #(clkper / 2) clk = ~clk;
32 end
33
34 initial begin
35 rst_n = 1'b1;
36 i_data_in = 1'b0;
37
38 #75;
39 i_data_in = 1'b1;
40
41 #100;
42 i_data_in = 1'b0;
43
44 #125;
45 i_data_in = 1'b1;
46
47 #75;
48 i_data_in = 1'b0;
49
50 #175;
51 i_data_in = 1'b1;
52
53 #25;
54 i_data_in = 1'b0;
55 end
56
57 endmodule
34行到55行

initial begin
rst_n = 1'b1;
i_data_in = 1'b0;

#75;
i_data_in = 1'b1;

#100;
i_data_in = 1'b0;

#125;
i_data_in = 1'b1;

#75;
i_data_in = 1'b0;

#175;
i_data_in = 1'b1;

#25;
i_data_in = 1'b0;
end
這種方式的優點是都在一個initial block，但有時候你可能已經很清楚絕對時間該產生什麼波形，為了這種寫法你必須去算相對時間。

使用絕對時間指定波形

1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com 3
4 Filename : posedge_detection_tb2.v
5 Compiler : ModelSim-Altera 6.1g
6 Description : testbench of posedge_detection.v
7 Release : 07/09/2008 1.0
8 */
9
10 `timescale 1ns/10ps
11 module posedge_detection_tb2;
12
13 reg clk;
14 reg rst_n;
15 reg i_data_in;
16 wire o_rising_edge;
17
18 posedge_detection u0 (
19 .clk(clk),
20 .rst_n(rst_n),
21 .i_data_in(i_data_in),
22 .o_rising_edge(o_rising_edge)
23 );
24
25 parameter clkper = 100;
26 initial begin
27 clk = 1'b0;
28 end
29
30 always begin
31 #(clkper / 2) clk = ~clk;
32 end
33
34 initial begin
35 rst_n = 1'b1;
36 i_data_in = 1'b0;
37 end
38
39 initial #75 i_data_in = 1'b1;
40 initial #175 i_data_in = 1'b0;
41 initial #300 i_data_in = 1'b1;
42 initial #375 i_data_in = 1'b0;
43 initial #550 i_data_in = 1'b1;
44 initial #575 i_data_in = 1'b0;
45
46 endmodule
39到45行

initial #75 i_data_in = 1'b1;
initial #175 i_data_in = 1'b0;
initial #300 i_data_in = 1'b1;
initial #375 i_data_in = 1'b0;
initial #550 i_data_in = 1'b1;
initial #575 i_data_in = 1'b0;
乍看之下，會覺得這種方是蠻笨的，他靠的是每個initial都是在#0執行的特色，所以能使用絕對時間。請參考(筆記) initial的幾個特色 (SOC) (Verilog)。

See Also
(筆記) 如何設計邊緣檢測電路? (SOC) (Verilog)
(筆記) initial的幾個特色 (SOC) (Verilog)