(原創) 是否該將所有Verilog檔都加入到Quartus II project中? (IC Design) (Quartus II)
2008-04-04 10:59
423 查看
Abstract
在Visual Studio中,所有要編譯的.cpp檔一定要加入project中才可編譯,但在Quartus II中,似乎不加入.v到project也能順利編譯,到底該將所有.v檔加入Quartus II project嗎?
Introduction
Quartus II也有project的機制,但實務上會發現,不需將.v檔加入project檔,Quartus II也能順利編譯,在Altera原廠所提供的Quartus II Introduction Using Verilog Design P.12中提到:
We should mention that in many cases the Quartus II software is able to automatically find the right files to use for each entity referenced in Verilog code, even if the file has not been explicitly added to the project. However, for complex projects that involve many files it is a good design practice to specifically add the needed files to the project.
翻成中文如下:
我們必須附帶說明,在很多情況下,Quartus II會自動根據Verilog程式中所參考的entity找到合適的檔案,即使這些檔案並未明確地加入project中。然而,在包含很多檔案的複雜project中,明確地將需要的檔案加入到project中是一個好編程習慣。
Reference
Quartus II Introduction Using Verilog Design
在Visual Studio中,所有要編譯的.cpp檔一定要加入project中才可編譯,但在Quartus II中,似乎不加入.v到project也能順利編譯,到底該將所有.v檔加入Quartus II project嗎?
Introduction
Quartus II也有project的機制,但實務上會發現,不需將.v檔加入project檔,Quartus II也能順利編譯,在Altera原廠所提供的Quartus II Introduction Using Verilog Design P.12中提到:
We should mention that in many cases the Quartus II software is able to automatically find the right files to use for each entity referenced in Verilog code, even if the file has not been explicitly added to the project. However, for complex projects that involve many files it is a good design practice to specifically add the needed files to the project.
翻成中文如下:
我們必須附帶說明,在很多情況下,Quartus II會自動根據Verilog程式中所參考的entity找到合適的檔案,即使這些檔案並未明確地加入project中。然而,在包含很多檔案的複雜project中,明確地將需要的檔案加入到project中是一個好編程習慣。
Reference
Quartus II Introduction Using Verilog Design
相关文章推荐
- (原創) 如何使用SignalTap II觀察reg值? (IC Design) (Quartus II) (SignalTap II) (Verilog)
- (原創) 多工器MUX coding style整理 (SOC) (Verilog) (Quartus II)
- (原創) 硬體是如何加速軟體呢? (IC Design) (Verilog)
- (原創) 用HDL設計硬體有什麼優點? (IC Design) (Verilog)
- (原創) wire與reg的差異? (初級) (IC Design) (Verilog)
- (原創) 由C語言學習Verilog的思維轉換 (C/C++) (C) (IC Design) (Verilog)
- (原創) 如何破解Quartus II 7.2 SP3? (IC Design) (Quartus II) (Nios II)
- (原創) 如何在DE2執行Checksum Master範例? (IC Design) (DE2) (Quartus II) (Nios II) (SOPC Builder)
- (筆記) 如何讓所有project共用Verilog PLI的dll? (SOC) (Verilog PLI)
- (原創) DE2-70能玩些什麼? (SOC) (Verilog) (Quartus II) (SOPC Builder) (Nios II) (μC/OS-II) (DE2-70)
- (原創) Verilog入門書籍推薦:Verilog數位電路設計範例寶典(基礎篇) (IC Design) (Verilog)
- (原創) 如何產生50MHz的時脈? (IC Design) (Verilog)
- (原創) 如何使用Nios II C2H compiler? (IC Design) (DE2) (Nios II) (Quartus II) (SOPC Builder) (C/C++) (C2H)
- (原創) 如何使用硬體 + μC/OS-II 的方式『播放SD卡內wav檔音樂』? (IC Design) (DE2) (Quartus II) (Nios II) (μC/OS-II)
- (原創) 如何成功執行『Using μC/OS-II RTOS with the Nios II Processor Tutorial』? (IC Design) (Quartus II) (Nios II) (μC/OS-II)
- (原創) 如何使用integer型別? (IC Design) (Verilog)
- (原創) Verilog入門書推薦2:數位系統實習 Quartus II (SOC) (Verilog)
- (原創) 如何使用SignalTap II觀察reg與wire值? (SOC) (Verilog) (Quartus II) (SignalTap II)
- (原創) 物件導向技術不只用在軟體開發而已,一樣也適用在系統晶片開發 (IC Design) (Verilog) (OO)
- (原創) 無號數及有號數的乘加運算電路設計 (IC Design) (Verilog) (OS) (Linux)