June 13th Wednesday (六月　十三日　水曜日)

  At Thumb mode we can use the registers is just a sub-set of those register at ARM mode.  We can
use eight registers(R0~R7), PC, SP, LR and CPSR.  At once at every privillege mode there are a group
of SP, LR and SPSR can be used by us.  As matter of a fact, R8 ~ R12 those registers can not be used
freely.  At Thumb mode, they are not standard registers there are little instructions can access them.

  In CPSR, there are four conditional flags which is from 31 bit to 28 bit.

  * N - Negative / Less than
  * Z - Zero
  * C - Carry / Borrow / Extend
  * V - Overflow

  At ARM mode most of instructions is runned with conditions.  But at Thumb mode only those conditional
instructions used those flags.

  In low 8 bits of CPSR there are four kinds of flags.

  * I = 1 - disable IRQ
  * F = 1 - disable FIQ
  * T - it reflex the status of process.
    For over version 5 and T series processes, this bit is 1, it means an application is running at
Thumb mode, otherwise, at ARM mode;
    For over version 5 and non-T series processes, this bit is 1, it means next instruction will cause
    a exception,
    mode, otherwise, at ARM mode.
  * M - M[4:0]: M0, M1, M2, M3, M4.

M[4:0]    Mode                 Accessible Registers
10000     User                 PC, R14 to R0, CPSR
10001     FIQ                  PC, R14_fiq to R8_fiq, R7 to R0, CPSR, SPSR_fiq
10010     IRQ                  PC, R14_irq, R13_irq,R12 to R0, CPSR, SPSR_irq
10011     SVC                  PC, R14_svc, R13_svc,R12 to R0, CPSR, SPSR_svc
10111     Abort                PC, R14_abt, R13_abt,R12 to R0, CPSR, SPSR_abt
11011     Undef                PC, R14_und, R13_und,R12 to R0, CPSR, SPSR_und
11111     System               PC, R14 to R0, CPSR (Architecture 4 only)

  There are some reserved bits.  They can not be used to store data.

Exception type                                     Exception mode      Vector address
Reset                                              Supervisor          0x00000000
Undefined instructions                             Undefined           0x00000004
Software Interrupt (SWI)                           Supervisor          0x00000008
Prefetch Abort (Instruction fetch memoryabort)     Abort               0x0000000c
Data Abort (Data Access memory abort)              Abort               0x00000010
IRQ (Interrupt)                                    IRQ                 0x00000018
FIQ (Fast Interrupt)                               FIQ                 0x0000001c

  Address 0x14  (omitted from the above table) holds the Address Exception vector, which is only
used when the processor is configured for a 26-bit address space.