基于CPLD的数字钟设计(二)

把代码改了一下，编译通过了，接下来得做仿真，除错了。呵呵，新手，自己鼓励一下自己！

/*+FHDR--------------------------------------------------------
file name: clock.v
Author: Clarke.Lee
E-mail: clarke.lee@163.com
--------------------------------------
Clock: 1hz
Reset: Synchronous,Low
include: counter60.v
counter24.v
--------------------------------------
Keywords: Counter, Digital Clock
//-FHDR---------------------------------------------------------*/

`timescale 1ns/1ns
`include "counter60.v"
`include "counter24.v"
`include "sel.v"

module clock(clk,
fm_key,
fh_key,
reset,
h,
m,
s);

input clk;
input fm_key;
input fh_key;
input reset;
output [4:0] h;
output [6:0] m;
output [6:0] s;

counter60 counters (.clk(clk),
.reset(reset),
.cout(cout_s),
.out(s));

counter60 counterm (.clk(clkm),
.reset(reset),
.cout(cout_m),
.out(m));

counter24 counterh (.clk(clkh),
.reset(reset),
.cout(cout_h),
.out(h));

sel selm (.a(clk),
.b(cout_s),
.f(clkm),
.sel(fm_key));

sel selh (.a(clk),
.b(cout_m),
.f(clkh),
.sel(fh_key));

endmodule

/*+FHDR--------------------------------------------------------
file name: counter60.v
Author: Clarke.Lee
E-mail: clarke.lee@163.com
--------------------------------------
include: counter6.v
counter10.v
--------------------------------------
Keywords: Counter
//-FHDR---------------------------------------------------------*/

`timescale 1ns/1ns
`include "counter6.v"
`include "counter10.v"

module counter60(clk,
reset,
cout,
out);

input clk;
input reset;
output cout;
output [6:0] out;

wire cout_6;
wire cout_10;
wire [2:0] out_6;
wire [3:0] out_10;

counter6 counter6_1 (.clk(clk),
.reset(reset),
.cout(cout_6),
.out(out_6));
counter10 counter10(.clk(cout_6),
.reset(reset),
.cout(cout),
.out(out_10));

assign out = {out_6,out_10};

endmodule

//-FHDR---------------------------------------------------------*/

`timescale 1ns/1ns
`include "counter6.v"
`include "counter4.v"

module counter24(clk,
reset,
cout,
out);

input clk;
input reset;
output cout;
output [4:0] out;

wire cout_6;
wire cout_4;
wire [2:0] out_6;
wire [1:0] out_4;

counter6 counter6_0 (.clk(clk),
.reset(reset),
.cout(cout_6),
.out(out_6));
counter4 counter4 (.clk(cout_6),
.reset(reset),
.cout(cout),
.out(out_4));

assign out = {out_6,out_4};

endmodule

/*+FHDR--------------------------------------------------------
file name: counter6.v
Author: Clarke.Lee
E-mail: clarke.lee@163.com
--------------------------------------
Keywords: Counter
//-FHDR---------------------------------------------------------*/

`timescale 1ns/1ns

module counter6(clk,
reset,
cout,
out);

input clk;
input reset;
output cout;
output [2:0] out;

reg cout;
reg [2:0] out;

reg [2:0] counter;

always@(posedge clk)
if(!reset)
out <= 0;
else
for(counter=1;counter<6;counter=counter+1)
out <= counter;

endmodule

/*+FHDR--------------------------------------------------------
file name: counter10.v
Author: Clarke.Lee
E-mail: clarke.lee@163.com
--------------------------------------
Keywords: Counter
//-FHDR---------------------------------------------------------*/

`timescale 1ns/1ns

module counter10(clk,
reset,
cout,
out);

input clk;
input reset;
output cout;
output [3:0] out;

reg cout;
reg [3:0] out;

reg [3:0] counter;

always@(posedge clk)
if(!reset)
out <= 0;
else
for(counter=1;counter<10;counter=counter+1)
out <= counter;

endmodule

/*+FHDR--------------------------------------------------------
file name: counter4.v
Author: Clarke.Lee
E-mail: clarke.lee@163.com
--------------------------------------
Keywords: Counter
//-FHDR---------------------------------------------------------*/

`timescale 1ns/1ns

module counter4(clk,
reset,
cout,
out);

input clk;
input reset;
output cout;
output [1:0] out;

reg cout;
reg [1:0] out;

reg [1:0] counter;

always@(posedge clk)
if(!reset)
out <= 0;
else
for(counter=1;counter<4;counter=counter+1)
out <= counter;

endmodule

/*+FHDR--------------------------------------------------------
file name: sel.v
Author: Clarke.Lee
E-mail: clarke.lee@163.com
--------------------------------------
Keywords: select devise
//-FHDR---------------------------------------------------------*/

`timescale 1ns/1ns

module sel(a,
b,
f,
sel);
input a;
input b;
input sel;
output f;

assign f = (a||sel)&(!sel||b);

endmodule